Infineon Technologies Ag

Robert Boschgmbh

Hannes Estl

Jens Barrenscheen

Axel Aue

Peter Rohm

Jens Graf

Herman Roozenbeek

Marie Denison

Angela Rohm, Legal Representative

Hermann Roozenbeek

Jens Dr Barrenscheen

A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.

Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto

An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.

A quasi-vertical semiconductor component in which, by variation of the layout, the process or the wiring of inner cells, a compensation for a voltage drop along a buried layer is provided in order thus to ensure a similar operating point of the individual inner cells in the well. Therefore, the disadvantages brought about by a voltage drop in the buried layer are ultimately overcome.

Quasi-vertical semiconductor component

Growing community of inventors

Munich, Germany

Hannes Estl