Infineon Technologies Ag

Infineon Technologies Austria Ag

Hannes Eder

Edward Fuergut

Manfred Engelhardt

Alexander Heinrich

Gunther Mackh

Markus Menath

Katharina Umminger

Reinhard Hess

Gabriel Maier

Ralf Otremba

Ivan Nikitin

Manfred Schneegans

Hans-Joerg Timme

Irmgard Escher-Poeppel

Alexander Komposch

Paul Ganitzer

Stefan Woehlert

Karsten Guth

Daniel Kraft

Bernd Roemer

Jens Goerlich

A method of producing a semiconductor device is provided. The method includes: providing a semiconductor wafer, the wafer including an upper layer of a semiconductor material, an inner etch stop layer and a lower layer; forming a plurality of functional areas in the upper layer; performing a selective first etch process on the upper layer so as to separate the plurality of functional areas from each other by trenches etched through the upper layer, the first etch process being substantially stopped by the inner etch stop layer; and removing the lower layer by a second etch process, the second etch process being substantially stopped by the inner etch stop layer.

Method of producing a semiconductor device and a semiconductor device

A method of forming a thinned encapsulated chip structure, wherein the method comprises providing a separation structure arranged within an electronic chip, encapsulating part of the electronic chip by an encapsulating structure, and thinning selectively the electronic chip partially encapsulated by the encapsulating structure so that the encapsulating structure remains with a larger thickness than the thinned electronic chip, wherein the separation structure functions as a thinning stop.

Thinning in package using separation structure as stop

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

A method of processing a plurality of packaged electronic chips being connected to one another in a common substrate is provided, wherein the method comprises etching the electronic chips, detecting information indicative of an at least partial removal of an indicator structure following an exposure of the indicator structure embedded within at least a part of the electronic chips and being exposed after the etching has removed chip material above the indicator structure, and adjusting the processing upon detecting the information indicative of the at least partial removal of the indicator structure.

Removable indicator structure in electronic chips of a common substrate for process adjustment

A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Device including a semiconductor chip and a carrier and fabrication method

A semiconductor chip () is provided having an adhesion-promoting-layer-free three-layer metallization (). The three-layer metallization () has an aluminum layer () applied directly on the semiconductor chip (), a diffusion barrier layer () applied directly on the aluminum layer (), and a solder layer () applied directly on the diffusion barrier layer (). Ti, Ni, Pt or Cr is provided as the diffusion barrier layer () and a diffusion solder layer is provided as the solder layer (). All three layers are applied by sputtering in a process sequence.

Semiconductor chip, semiconductor device and methods for producing the same

Growing community of inventors

Villach, Austria

Hannes Eder