National Applied Research Laboratories

Taiwan Semiconductor Manufacturing Comp. Ltd.

National Chip Implementation Center National Applied Research Laboratories

Seoul National University

National Chip Implementation Center

Hann-Huei Tsai

Ying-Zong Juang

Chin-Fong Chiu

Chih-Yuan Yeh

Po-Chang Wu

Chen-Fu Lin

Sheng-Hsiang Tseng

Kuei-Cheng Lin

Chung-Te Lin

Yu-Chen Liu

Chin-Chia Kuo

Chih-Cheng Hsieh

Chin-Hsiung Ho

Chin-Long Wey

Jia-Ren Chen

Chia-Hsin Lee

Kuo-Wei Cheng

Wen-Hsu Chang

You-Liang Lai

Li-De Hsu

Yuan-Ta Hsieh

Jian Li

Yi-Jen Wang

Bo-You Liu

Hsin-Hao Liao

This invention provides a light-concentrating structure with photosensitivity enhancing effect, including the substrate, buried layer, first electrode layer, second electrode layer, dielectric layer and interconnection structure. The substrate is equipped with a housing space; the buried layer is arranged above the substrate with the housing space; the first electrode layer is arranged above the buried layer; the second electrode layer is arranged in the middle of the first electrode layer; the dielectric layer is arranged above the second electrode layer; the interconnection structure is arranged above the substrate and the first electrode layer surrounding the dielectric layer, which forms an opening and a light-concentrating recess groove.

Light-concentrating structure with photosensitivity enhancing effect

A signal error calibrating method is disclosed herein and includes following steps: filtering an error voltage in a sensor by a low pass filter in a calibration mode; converting the offset voltage to be a digital offset signal by an analog digital signal converter; converting the digital offset signal to be an offset calibrating signal by a digital analog signal converter; transmitting the offset calibrating signal to an input end of the sensor so as to offset an error voltage at the input end of the sensor. After calibrating the error voltage, the analog digital converter in the error calibrating circuit can be used for the need of signal output and the low pass filter is turned off at the same time.

Signal error calibrating method

A signal process circuit includes a signal modulation unit, a first resistor, a second resistor, a first discharge unit, a second discharge unit and a discharge detection unit. The signal modulation unit is used to modulate an input signal for generating a modulated signal. The first resistor is coupled between the signal modulation unit and an operation node. The second resistor is coupled between the operation node and the signal modulation unit. The first discharge unit is coupled to the signal modulation unit. The discharge unit is coupled to the signal modulation unit. The discharge detection unit is coupled to the first discharge unit, the operation node and the second discharge unit for detecting an output common voltage and control a discharge path accordingly.

Signal process circuit capable of being externally coupled to multiple types of amplifier circuits

The present invention discloses a monolithic z-axis torsional CMOS MEMS accelerometer, it includes a matching frame, two anchors, a first comb structure, a second comb structure and a proof mass. With the implementation of the present invention, the capacitance sensitivity of Z+ direction and Z&#x2212; direction sensing signals by the accelerometer can be improved. On the other hand, due to the feasibility of applying micromachining etch processes from the top side, the ease and the yield of production are both promoted.

Monolithic z-axis torsional CMOS MEMS accelerometer

The invention includes two parallel paths. A first path is composed of two contact ends of a first electronic switch and a first, third and fifth diodes, which connect in series. One contact end connects a first end of an AC source, and a control end connects a second end of the AC source. A second path is composed of two contact ends of a second electronic switch and a second, fourth and sixth diodes, which connect in series. One contact end connects the second end of the AC source, and a control end connects the first end of the AC source. The AC source is connected between the positive ends of the first and second diodes. The second end of the AC source separately connects negative ends of the first and third diodes through two capacitors. The first end of the AC source separately connects negative ends of the second and fourth diodes through another two capacitors. Negative ends of the fifth and sixth diodes connect together to form a voltage output end.

Master-slave voltage doubling full-wave rectifier for wireless power transfer system

A current-steering offset compensation circuit is configured for compensating an offset caused by process variation or environment variation of a signal processor. The signal processor includes a pair of differential input terminals and a pair of differential output terminals. The current-steering offset compensation circuit comprises a current-steering circuit connected with the signal processor, a digital control unit which generates a digital control signal according to the outputs from the pair of differential output terminals of the signal processor, and a digital-to-analog converter which receives the digital control signal and outputs a control voltage, wherein the current-steering circuit receives the control voltage, so as to steer the current of the pair of differential input terminals, to reduce the offset in the signal processor.

Offset compensation circuit and method thereof

The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved.

Circuit sharing time delay integrator

A structure for a metal-oxide-semiconductor field-effect transistor (MOSFET) sensor is provided. The structure includes a MOSFET, a sensing membrane, and a reference electrode. The reference electrode and the sensing membrane are formed on the first surface of the MOSFET and are arranged in such a way that the reference electrode and the sensing membrane are uniformly and electrically coupled to each other. Thus, the electric field between the sensing membrane and the reference electrode is uniformly distributed therebetween to stabilize the working signal of the MOSFET sensor.

Structure for MOSFET sensor

A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified.

Hydrogen ion-sensitive field effect transistor and manufacturing method thereof

A CMOS-MEMS switch structure is disclosed. The CMOS-MEMS switch structure includes a first substrate, a second substrate, a first cantilever beam, and a second cantilever beam. The first and second substrates are positioned opposite each other. The first cantilever beam is provided on the first substrate, extends from the first substrate toward the second substrate, and bends downward. Likewise, the second cantilever beam is provided on the second substrate, extends from the second substrate toward the first substrate, and bends downward. The first and second substrates are movable toward each other to connect a first top surface of the first cantilever beam and a second top surface of the second cantilever beam, and away from each other so that the first top surface of the first cantilever beam and the second top surface of the second cantilever beam are disconnected, thereby closing or opening the CMOS-MEMS switch structure.

CMOS-MEMS switch structure

A biosensor package structure with a micro-fluidic channel is provided. The biosensor package structure includes a substrate, a biochip, and a cover. The substrate has a first surface, a second surface, and an opening. The biochip is attached on the first surface. A bio-sensing area of the biochip is exposed to the opening of the substrate. The cover is attached on the second surface to cover the opening so as to form a micro-fluidic channel. By implementing the invention, the manufacturing process of the biosensor is simplified and the productivity is increased.

Biosensor package structure with micro-fluidic channel

A method and apparatus for performing a semiconductor process wafer drying process, the method provides a semiconductor wafer having a process surface disposed in an enclosed drying space following exposure of the process surface to water; supplying a solvent vapor to the drying space at a predetermined concentration from a solvent vapor source and at least one solvent vapor supply line; determining at least one of a solvent vapor concentration and a solvent vapor temperature in the drying space; and heating in response to the determined solvent concentration at least one of at least a portion of one of the solvent vapor source, the at least one solvent vapor supply line, and at the drying space to alter the solvent vapor concentration in the drying space.

Method to improve post wafer etch cleaning process

A method for fabricating shallow trench isolation stricture wherein a surface oxide layer and a polycrystalline silicon buffer layer are formed on a semiconductor body. Openings are formed through the layers and into the body that constitute trenches. A lining oxide layer is formed on the trench and buffer layer surfaces. A thick oxide layer is deposited on the body to fill the trench, and the layer planarized by chemical-mechanical polishing. The exposed portions of the buffer layer are removed and the horizontal surface oxide layer portions removed by anisotropic etching.

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Hsinchu, Taiwan

Hann-Huei Tsai