Samsung Electronics Co., Ltd.

Seoul National University

Hanmin Park

Hyung-Dal Kwon

Jae-Eon Jo

Jaehyeong Sim

Seungwon Lee

Seungwook Lee

Kiyoung Choi

Namhyung Kim

Seung Wook Lee

Ho Young Kim

Gunhee Lee

Joonsang Yu

A processor-implemented method of processing neural network data includes: setting first limit data by performing a first operation based on first input data and weight data generated from weights included in a filter; comparing the first limit data with an intermediate result of a second operation performed based on second input data and the weight data; and determining whether to perform a subsequent second operation based on a result of the comparing.

Method and apparatus with data processing

An apparatus with deep learning includes: a systolic adder tree including adder trees connected in row and column directions; and an input multiplexer connected to an input register of at least one of the adder trees and configured to determine column directional data movement between the adder trees based on operation modes.

Method and apparatus with deep learning operations with adder tree structure

A method of accelerating a training process of a neural network includes acquiring activations used in the training process and a bit-vector corresponding to the activations, selecting activations requiring an operation from among the acquired activations by using the bit-vector, and performing backward propagation using the selected activations and filters corresponding to the selected activations.

Method of accelerating training process of neural network and neural network device thereof

A computing device and method is disclosed. The computing device includes a plurality of processing cores, and a tile scheduler configured to update a cost matrix of each of the plurality of processing cores based on meta information of each of first tiles previously allocated to the plurality of processing cores and meta information of each of second tiles, and allocate the second tiles with respect to the plurality of processing cores using the updated cost matrix of each of the plurality of processing cores.

Computing device and method for allocating resources using cost matrix

An accelerator, a method of operating the accelerator, and an electronic device including the accelerator. A method of operating the accelerator configured to perform a target operation includes packing input data with a data layout determined based on a word width of a memory in the accelerator and a spatial size of a filter to be applied to the target operation and storing the packed input data in the memory, and performing the target operation between a portion of the input data stored in a same word in the memory and weights of the filter.

Accelerator, method of operating an accelerator, and electronic device including an accelerator

Disclosed is an apparatus and method for performing deep learning operations. The apparatus includes a systolic array comprising multiplier accumulator (MAC) units, and a control circuit configured to control an operation of a multiplexer connected to at least one of the MAC units and operations of the MAC units according to a plurality of operation modes.

Growing community of inventors

Seoul, South Korea

Hanmin Park