Samsung Electronics Co., Ltd.

Hanmei Choi

Kihyun Hwang

Chanjin Park

Sunghoi Hur

Kwangmin Park

Toshiro Nakanishi

Wansik Hwang

Kwang Soo Seol

Juyul Lee

Bongjin Kuh

Seung Hyun Lim

Dongchul Yoo

Young Woo Park

Woo Sung Lee

Jae Duk Lee

Dong Seog Eun

Jong Won Kim

Chang Seok Kang

Jae Woo Lim

Dae Hoon Bae

Jung Ho Kim

Hyung Joon Kim

Yong-Hoon Son

Bio Kim

Taegon Kim

Jae Young Ahn

Junkyu Yang

Sukjin Chung

Gyungjin Min

Juyeon Kim

Joonghan Shin

Yoochul Kong

Young Seon Son

Ju Mi Yun

Changyong Kim

Hakyu Seong

Jongsung Lim

Su Jin Shin

Ki-chul Kim

Ki-Hyun Hwang

Beom Seok Kim

Sungho Kang

Jae Young Park

Kwang-Soo Seol

Kichul Kim

Jeonggil Lee

Seong Hoon Jeong

Hauk Han

SeungHyun Lim

Woosung Lee

Soodoo Chae

Jong-Hoon Kang

Kyoungseob Kim

Byong-Hyun Jang

Sangryol Yang

Shinjae Kang

Hong Bum Park

Ju-Yul Lee

Soonwook Jung

JeongMeung Kim

Youngsub You

Byunghong Chung

Eunyoung Jo

Gonsu Kang

Sungho Heo

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Three-dimensional semiconductor memory devices and methods of fabricating the same

A semiconductor device includes a plurality of patterns defined between a plurality of trenches and disposed on a substrate. A leaning control layer is disposed on sidewalls and bottoms of the plurality of trenches. A gap-fill insulating layer is disposed on the leaning control layer. At least one of the plurality of trenches has a different depth from one of the plurality of trenches adjacent thereto.

Semiconductor device including trench isolation layer and method of forming the same

Semiconductor devices including a substrate including a cell array region and a through electrode region, an electrode stack on the substrate and including electrodes, vertical structures penetrating the electrode stack within the cell array region, vertical fence structures within an extension region and surrounding the through electrode region, and insulating layers being inside a perimeter defined by the vertical fence structures and being at the same level as the electrodes may be provided. The electrodes may include first protrusions protruding between the vertical fence structures in a plan view.

Semiconductor device having vertical fence structures

A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

Nonvolatile semiconductor devices including non-circular shaped channel patterns and methods of manufacturing the same

A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.

Semiconductor device

A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

Vertical memory devices having dummy channel regions

A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.

Semiconductor devices including gate dielectric structures

A semiconductor device includes a substrate, a first insulation layer formed on the substrate in a first region, a photon absorption seed layer formed on the first insulation layer in the first region and on the substrate in a second region separate from the first region, and a photon absorption layer formed on the photon absorption seed layer in the first region. The photon absorption seed layer has a particular structure that may assist in reducing dislocation density in a region that includes a photon absorption layer.

Semiconductor device and method for fabricating the same

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Seoul, South Korea

Hanmei Choi