Synopsys, Inc.

Hanish Singla

Eduard Rudolf Cerny

Dmitry Korchemny

Sudipta Kundu

Ashok Kumar Bhatt

Nishant Chauhan

A method or system for clock gating verification of a circuit design. The system identifies a set of sequential components of the circuit design, and a set of nets of the circuit design. Each net is configured to provide a signal to a clock pin of a sequential component. The system then identifies a subset of nets that are associated with toggle signals, each of which transitions between two different signal values. For each of the subset of nets, the system determines one or more toggle cover properties. The system also determines a depth of at least one net in the subset of nets, and performs sign off for the clock gating verification based on the toggle cover properties and the depth of the at least one net.

Performing automatic sign-off for clock gating verification using toggle cover properties

Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.

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Uttar Pradesh, India

Hanish Singla