Amazon Technologies, Inc.

Hani Ayoub

Adi Habusha

Ronen Shitrit

Nafea Bshara

Anthony Nicholas Liguori

Matthew Shawn Wilson

Barak Wasserstrom

Brian William Barrett

Clint Joseph Sbisa

Itay Poleg

Darin Lee Frink

Leah Shalev

Avigdor Segal

Christopher James BeSerra

Ziv Harel

Shadi Ammouri

Yossi Leybovich

Yehuda Yitschak

Talor Kovary

Saleh Abd-Alhaleem

A different network address is assigned to each port of a first device and a second device that are configured to exchange traffic over a multi-path connection of a transport layer protocol. When a timeout is detected by the first device indicating that a packet sent to a first network address assigned to a first port of the second device was not received, the first device can regenerate the packet with a second network address assigned to a second port of the second device, and send the regenerated packet to the second network address of the second device. The first device can send heartbeat packets to the first port in an exponential backoff manner and, upon receiving a heartbeat acknowledgement from the first port, resume sending the packets to the first port.

Multi-port load balancing using transport protocol

Communication in an asymmetric multiengine system is handled using engine routing tables defining subsets of engines to control engine-to-engine connection mapping. Local devices perform an engine selection process that includes selecting an engine routing table based on a number of remote engines in a remote device and selecting an engine set from the selected table based on an identifier of the remote device. A connection to the remote device is created using the engines identified in the selected engine set.

Symmetric communication for asymmetric environments

Described herein is a hybrid approach to error reporting, using a combination of hardware and software, for peripheral component interconnect (PCI) express devices. The device hardware detects an error on a packet, where the packet is for a transaction and received from a host computer. Upon detecting the error, the device hardware generates an interrupt that is processed in software. In certain embodiments, the software based processing involves determining, based on the packet, that the transaction is directed to an address space of an emulated configuration register. The software based processing further involves identifying a function as being associated with the error, determining attributes associated with the error, and storing the attributes and an identifier associated with the function in a location available to the device hardware, thereby enabling the device hardware to report the attributes and identifier to the host computer.

Hybrid hardware and software reporting management

A hybrid approach using hardware and software is used for report management in peripheral component interconnect (PCI) express devices. The device hardware detects an error associated with a transaction with a host computer. The device software identifies a function associated with the error and determines various attributes of the error. The device software then exposes the attributes of the error in the PCI express and the advanced error reporting (AER) capabilities. The error can be reported in a message transaction to the host computer.

Techniques for updating code of a device may be described. In an example, bus may connect the device to a management entity. The device may run a first version of the code. A second version of the code may be available from memory. The device may access the second version from the memory, stop running the first version of the code, and start running the second version of the code without restarting the management entity or the device.

Updating device code through a bus

A method of transferring data between a host and a PCI device is disclosed. The method comprises mapping a fixed memory-mapping control block in a host memory of the host to a control register of a memory-mapping unit of the PCI device; mapping a dynamic data-access memory block in the host memory to a default memory block in a memory of the PCI device, wherein the memory-mapping unit translates an address between the dynamic data-access memory block and a memory block in the memory of the PCI device; and dynamically modifying a value in the control register of the memory-mapping unit through the fixed memory-mapping control block such that an address of the dynamic data-access memory block in the host memory is translated to a different address in the memory of the PCI device based on the modified value in the control register of the memory-mapping unit.

Device full memory access through standard PCI express bus

Provided are systems and methods for a location-aware, self-configuring peripheral device. In some implementations, the peripheral device may include two or more personalities. In these implementations, a personality enables the peripheral device to provide a service. In some implementations, the peripheral device may be configured to receive a configuration cycle. In some implementations, the peripheral device may further select a personality from among two or more personalities. The peripheral device may use information derived from the configuration cycle to make this selection. Selecting a personality may further include configuring the peripheral device according to the selected personality.

Growing community of inventors

Majd al-Krum, Israel

Hani Ayoub