Apple Inc.

Hang Huang

Brian J Campbell

Greg M Hess

Ajay Bhatia

Daniel C Chow

Steven C Sullivan

Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may be configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

Write driver circuit with low voltage bootstrapping for write assist

A voltage source controller for a memory array includes an input coupled to a voltage source, an output coupled to one or more memory cells of a memory array, where the output is configured to provide a cell source voltage to the memory cells. The controller also includes a switch circuit configured to: receive a retention enable signal, a write assist enable signal, and a standard mode enable signal; and based on the retention enable signal, write assist enable signal, and standard mode enable signal, selectively set the cell source voltage for one or more of the memory cells to one of: a retention voltage, a write assist voltage, or a standard mode voltage, where the retention voltage and the write assist voltage are less than the standard mode voltage.

Memory array voltage source controller for retention and write assist

In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, including one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by a control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.

Leakage and NBTI reduction technique for memory

In one embodiment, an integrated circuit includes a logic circuit and a memory circuit that includes multiple bit lines and bit line precharge circuits. The memory circuit may include level shifters for control signals generated from logic circuit inputs, and particularly there may be one or more level shifters that generate precharge enable signals to control the bit line precharge circuits. The level shifters for the bit line precharge circuits may also be controlled, during periods of time that the memory circuit is idle, by an input control signal (FloatBL herein). If the FloatBL signal is asserted, the bit line precharge circuits may be disabled to float the bit lines. In some embodiments, the FloatBL signal may also disable bit line bit line hold circuits on the bit lines. In some embodiments, when the memory circuit is exiting an idle state, the bit line precharge circuits may be enabled in a staggered fashion.

In one embodiment, a memory circuit includes one or more memory cells that include transistors having a first nominal threshold voltage, and interface circuitry such as word line drivers and bit line control circuitry that includes one or more transistors having a second nominal threshold voltage that is lower than the first nominal threshold voltage. For example, the word line driver circuit may be driven by signals from a lower voltage domain than the memory circuit's voltage domain. Lower threshold voltage transistors may be used for those signals, in some embodiments. Similarly, lower threshold voltage transistors may be used in the write data driver circuits. Other bit line control circuits may include lower threshold voltage transistors to permit smaller transistors to be used, which may reduce power and integrated circuit area occupied by the memory circuits.

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Sunnyvale, CA, United States of America

Hang Huang