Qualcomm Incorporated

Hanfang Pan

Yongbin Wei

Michael Alexander Howard

Inyup Kang

Nischal Abrol

Simon Turner

Jian Lin

James Krysl

Peter S Gaal

Wanshi Chen

Durga Prasad Malladi

Aamod Dinkar Khandekar

June Namgoong

Parvathanathan Subrahmanya

Ke Liu

Qiang Shen

Wenqing Wu

Mariam Motamed

Nicholas K Yu

Deepak Mathew

Robert Fuchs

Safi Khan

Michael A Kongelf

Daniel T Macek

Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity. The UE may then prioritize the channel state processes and/or may transmit one or more non-current reports.

Channel state computation for enhanced carrier aggregation

Techniques for assigning multipaths to finger processors to achieve the desired data performance and low power consumption are described. A search is initially performed to obtain a set of multipaths for a transmission from at least one base station. At least one multipath (e.g., the minimum number of multipaths) having a combined performance metric (e.g., a combined SNR) exceeding a threshold is identified. The at least one multipath is assigned to, and processed by, at least one finger processor to recover the transmission from the base station(s).

Minimum finger low-power demodulator for wireless communication

A wireless communication signal in Long Term Evolution (LTE) may be interleaved in a manner which permits a partitioning of a received inter-column bit-reversed interleaved code block for improved de-interleaving. The code block may be divided into equal subportions which may be simultaneously de-interleaved both forward and backward, and in parallel with other subportions. An even number of subportions may be provided. Dividing a received code block in this manner may improve de-interleaving performance.

Method and apparatus for parallel de-interleaving of LTE interleaved data

Systems and methodologies are described that facilitate automatically generating interleaved addresses during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial and a modular function given interleaved parameters 'a' and 'b' from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.

Recursive realization of polynomial permutation interleaving

Efficient apparatus and method for Zadoff-Chu ('Chu') sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than N log 2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.

Efficient zadoff-chu sequence generation

Systems and methodologies are described that facilitate ensuring contention and/or collision free memory within a turbo decoder. A Posteriori Probability (APP) Random Access Memory (RAM) can be segmented or partitioned into two or more files with an interleaving sub-group within each file. This enables parallel operation in a turbo decoder and allows a turbo decoder to access multiple files simultaneously without memory access contention.

APP (a priori probability) storage design for LTE turbo decoder with quadratic permutation polynomial interleaver

Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

Efficient multi-symbol deinterleaver

An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, 'un-escaping' the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

HDLC hardware accelerator

A microprocessor system having an interrupt controller is provided for use in a mobile communications device. Peripheral processing units generate interrupt requests for sending to the microprocessor. The microprocessor has components for responding to interrupt requests by interrupting current processing and performing an interrupt service routine associated with the interrupt request. The interrupt controller receives interrupt requests directed to the microprocessor from the peripheral processing units and for prioritizes the interrupt requests on behalf of the microprocessor. By providing an interrupt controller for prioritizing interrupt requests on behalf of the microprocessor, the microprocessor therefore need not devote significant internal resources to prioritizing the interrupt request signals.

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Hanfang Pan