Mellanox Technologies, Ltd.

Hananel Faig

Yair Yakoby

Oz Harel

Raanan Ivry

Matan Groen

Anthony Eugene Zortea

Shai Cohen

Chen Gaist

Nir Sheffi

Boris Sharav

Liron Gantz

Alik Gorshtein

David (Dima) Rochlin

David Rohlin

David (Dima) Rohlin

Adam Kaminer

Mor Goren

A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to detect that an aggregate error level associated with the equalized signal exceeds a saturation threshold level. The decision generation component identifies a set of errors including a first error associated with a first symbol having a highest error level and a last error associated with a last symbol. The decision generation component generates, based on the equalized signal, a decision including a sequence of one or more bits that represent each symbol of a first subset of the sequence of symbols and a confidence level corresponding to the decision, where the confidence level is based at least in part on a distance between an error level of each symbol and a level of the first error.

Digital signal symbol decision generation with corresponding Forney-based confidence level

A receiver includes an analog-to-digital converter (ADC) to generate a digital output, including a set of bits corresponding to a received signal. The receiver further includes a calculator circuit coupled to the ADC, the calculator circuit to calculate a set of tap coefficient gradient values corresponding to the digital output, generate a first feedback signal corresponding to the set of tap coefficient gradient values, and generate a second feedback signal corresponding to the set of tap coefficient gradient values. The receiver further includes a clock data recovery (CDR) circuit, coupled to the calculator circuit, the CDR circuit to detect a first parameter of the received signal based on the first feedback signal. The receiver further includes a feed forward equalization (FFE) system, coupled to the calculator circuit, the FFE system including multiple filter taps having a set of filter tap coefficients to be adapted based on the second feedback signal to generate a set of adapted filter tap coefficients.

Clock and data recovery circuit and feed forward equalizer decoupling

A receiver including an equalization component to receive a signal comprising a sequence of samples corresponding to symbols and generate an equalized signal with an estimated sequence of symbols corresponding to the signal. The receiver further includes a decision generation component to receive the equalized signal and generate, based on the equalized signal, a decision comprising a sequence of one or more bits that represent each symbol of the sequence of symbols and a confidence level corresponding to the decision.

Digital signal symbol decision generation with corresponding confidence level

A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.

Analog-to-digital converter to identify properties of transmitted signals

A signal processing method includes receiving a digital signal including a sequence of samples. For each sample among at least some of the samples, a neighbor-based estimate is calculated over (i) one or more samples that precede the sample in the sequence and (ii) one or more samples that succeed the sample in the sequence, and an error value, indicative of a deviation of the neighbor-based estimate from an actual value of the sample, is calculating. An impairment in the digital signal is estimated based on a plurality of error values calculated for a plurality of the samples.

Impairment detector for digital signals

In some disclosed embodiments, a Decision Feedback Equalizer (DFE) processes multiple symbols in parallel using a novel architecture that avoids violating a timing constraint. The DFE comprises Feed-Back (FB) filters that can be configured to equalizing nonlinear phenomena. Using a Look-Up Table (LUT)-based implementation, the FB filters may implement complex nonlinear functions at low hardware complexity, low latency and low power consumption. A LUT-based implementation of the FB filter supports adaptive FB filtering to changing channel conditions by updating LUT content.

Parallel decision feedback equalizer partitioned for high throughput

A method for implementing an efficient clock recovery for multilane high-speed Serializer/Deserializer (SerDes) system having M interleaved lanes, has a non-recursive architecture.

Method and apparatus for performing clock and data recovery (CDR)

A method for providing back-compatibility for rational sampling rate disparities between two circuitries, comprises: a) providing a Phase Locked Loop (PLL) operating at a rate different than that of the Symbols generator, which is coupled to a Digital to Analog Converter (DAC) or an Analog to Digital Converter (ADC); b) providing an interpolation filter coupled to said converter, which filter is adapted to perform sampling rate conversion operations on the samples using zero-stuffing, filtering, and decimation, or the like computation-saving algorithm; and c) obtaining the sampling of the symbols at the required and compatible rate.

Method and apparatus for implementing multirate SerDes systems

A method for communication includes producing an error signal by comparing a driving signal applied to a transmitter to an output signal generated by the transmitter in response to the driving signal. The error signal is decomposed into a linear component having a first memory depth and a nonlinear component having one or more polynomial orders and a second memory depth that is less than the first memory depth. First coefficients, up to the first memory depth, of a linear predistortion kernel are computed for application to the driving signal so as to compensate for the linear component of the error signal. Second coefficients for the one or more polynomial orders, up to the second memory depth, of a nonlinear predistortion kernel are computed so as to compensate for the nonlinear component of the error signal. Operation of the transmitter is optimized using the first and second coefficients.

Compensating for transmitter nonlinearities

In one embodiment, a time-interleaved analog-to-digital convertor (ADC) system, includes an array of ADCs to sample respective analog voltages at sampling times indicated by respective clock signals and to output corresponding digital values, phase generator circuitry to provide multiple, different phase-shifted clock signals for driving the respective sampling times of the ADCs, and a clock and data recovery circuit including ADC-specific first-order loop filters to derive respective ADC-specific average phase error corrections, and a shared loop filter to derive a shared average phase error correction over the array of ADCs and wherein the phase generator circuitry is coupled to provide corrected respective ones of the phase-shifted clock signals responsively to both respective ones of the ADC-specific average phase error corrections derived by respective ones of the first-order loop filters, and the shared average phase error correction derived by the shared loop filter.

Growing community of inventors

Jerusalem, Israel

Hananel Faig