Densbits Technologies Ltd.

Avago Technologies General IP (singapore) Pte. Ltd.

Kioxia Corporation

Toshiba Memory Corporation

Avago Technologies International Sales Pte. Limited

Hanan Weingarten

Avi Steiner

Erez Sabbag

Michael Katz

Ofir Kanter

Yasuhiko Kurosawa

Shmuel Levy

Avigdor Segal

Amir Nassie

Ilan Bar

Ofir Avraham Kanter

Igal Maly

Eli Sterin

Eyal Nitzan

Meir Nadam-Olegnowicz

Evgeni Pinkovich

Anat Rot

Neil Buxton

Yasuyuki Ushijima

Alex Britva

Irena Shemesh

Liran Kost

Nimrod Bregman

Assaf Sella

Zion Nahisi

Guy Azrad

Alik Vainerovitch

Dani Pinkovich

A method for reading data from a solid-state drive (SSD) configured to store data in a plurality of memory cells arranged in memory blocks comprising rows, the method performed by a controller in communication with the plurality of memory cells. The method comprises retrieving data from a target row of memory cells of the plurality of memory cells associated with a read request received from a host using initial threshold voltages. The method also includes decoding the data using a hard decision stage. Additionally the method comprises estimating read threshold voltages of the target row of memory cells based on a transformation of a distribution of threshold voltages of cells in a memory block containing the target row when the hard decision decoding stage fails. The method further includes retrieving data from the target row using the estimated read threshold voltages.

Feature based read threshold estimation in NAND flash memory

One or more processors of a system may determine one or more program parameters of a plurality of rows of cells of a non-volatile memory, determine a first threshold of a first parameter of each row based on the one or more program parameters of the plurality of rows, determine, by changing a programming time of each row, a set of parameters of each row that causes the first parameter not to cross the first threshold, determine a second threshold of a second parameter of each row based on production statistics of a plurality of dies as a result of mass production, adjust the programming time of each row to cause the second parameter not to cross the second threshold, and program data to a first row of the plurality of rows using the set of parameters of the first row and the adjusted programming time of the first row.

System and method for determining optimal program parameters in non-volatile memory systems

Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

Method and system for error correction in memory devices using irregular error correction code components

Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

Hard decoding methods in data storage devices

A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

Bit error rate estimation and classification in NAND flash memory

Systems, methods, non-transitory computer-readable media configured to perform operations associated with a storage medium. One system includes the storage medium and an encoding/decoding (ED) system, the ED system being configured to receive a set of input log-likelihood ratios (LLRs) of a component of the plurality of components, determine an extrinsic estimation function based on a set of features of the set of input LLRs, analyze the extrinsic estimation function to obtain a plurality of extrinsic LLR values, map the plurality of extrinsic LLR values to an input LLR of the set of input LLRs, and output, for each component, a plurality of updated LLR values based on the mapping.

Deep neural network implementation for concatenated codes

A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

Efficient decoding schemes for error correcting codes for memory devices

A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain a first soft read sample by performing a first read operation on a location of the flash memory with a first reference voltage. The circuit may be configured to determine a second reference voltage based on the first soft read sample. The circuit may be configured to obtain a second soft read sample by performing a second read operation on the location of the flash memory with the second reference voltage. The circuit may be configured to generate soft information based on the first and second soft read samples. The circuit may be configured to decode a result of a third read operation on the location of the flash memory based on the soft information.

System and method for pre-soft-decoding tracking for NAND flash memories

Various implementations described herein relate to systems and methods for programming data, including determining a target row corresponding to a program command and setting row-based programming parameters for the target row using target physical device parameters of the target row and optimized programming parameters corresponding to the physical device parameters.

Generation of programming parameters for non-volatile memory device based on physical device parameters

A method for dynamically estimating interference compensation thresholds of a page of memory includes computing a histogram and a corresponding threshold based on a plurality of interference states of an interference source; clustering the plurality of interference states to determine an effective number of interference states; and estimating a read threshold to dynamically compensate an interference noise associated with each interference state of the effective number of interference states of the target row based on the histogram.

System and method for dynamic compensation for multiple interference sources in non-volatile memory storage devices

Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.

Decoding scheme for error correction code structure

A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.

System and method for high reliability fast RAID decoding for NAND flash memories

Various implementations described herein relate to systems and methods for encoding and decoding data having input payload stored in a non-volatile storage device, including encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, and decoding the plurality of encoded short codewords to obtain the data, where each of the plurality of short codewords corresponding to a portion of the input payload.

Growing community of inventors

Herzelia, Israel

Hanan Weingarten