Burroughs, Inc.

Other

Discovery Partners International, Inc.

Unisys Corporation

Irori

Scientific Computer Systems Corporation

Hanan Potash

Michael P Nova

Melvyn E Genter

Andrew E Senyei

Xiao-Yi Xiao

Burton L Levin

Bruce B Roesner

Chanfeng Zhao

Gary S David

Yozo Satoda

Zahra Parandoosh

Andrew E Phelps

Erick M Cook

John E Lillig

Howard H Green

William R Ewing

Stephen J Chan

William B Thompson

Jennifer S Schuh

Mark A Haakmeester

Kanchana Sanjaya Gunesekera Karunaratne

A computing device includes one or more processors and one or more memory devices. The computing device comprises a Civilware tier configured to perform one or more resource management functions in the computing device. In some embodiments, the Civilware tier includes a resource manager that is at least partially programmable to manage one or more functions in the computing device. The Civilware tier may enforce one or more rules of behavior in the computing device. In some embodiments, the computing device further includes an instructions interpretation tier. The rules enforced by the Civilware tier are independent of the specifics of the algorithms executed in the instruction interpretation tier (e.g., the Civilware tier is orthogonal to the instruction interpretation tier).

Computing device with resource manager and civilware tier

An electronic computer-aided design tool includes a design module and a printed electronics printer coupled to the design module. The design module determines one or more design specifications for an electronic device. The printed electronics printer produces one or more printed electronics prototypes of the electronic device based at least in part on at least on at least one of the design specifications. In some embodiments, the electronic computer-aided design tool includes a prototype testing unit that tests prototypes made by the printed electronics printer.

Electronic computer-aided design tool

A computing device includes a plurality of bins distributed in a plurality of frames, and a plurality of mentor circuits. The bins store information for variables. Each mentor circuit may be assigned to a particular one or more of the variables. The mentor circuits perform cache management and operand addressing operations with respect to the particular variables to which the mentor circuit is assigned. A control circuit controls a main program flow.

Enhanced security computer processor with mentor circuits

A computer processor includes an operands-mapped namespace and/or a Variables mapped namespace. In some embodiments, a system for performing computing operations includes a processor comprising a namespace; and one or more memory devices physically or logically connected to the processor, wherein the memory devices comprise memory space. The namespace of the processor is not limited to the memory space of the one or more memory devices. In an embodiment, a method of computing includes physically or logically connecting a processor to one or more memory devices comprising memory space, and implementing, by the processor, a namespace, in which the namespace is not limited to the memory space to which the memory space is physically or logically connected.

Computer processor with operand/variable-mapped namespace

A computing device includes a main memory; a local high speed memory; one or more functional units, one or more interconnects between the main memory and the local high speed memory, and one or more interconnects between the local high speed memory and the one or more functional units. The local high speed memory implements a frames/bins structure. The local high speed memory includes a plurality of frames, each of at least two of the frames comprising a physical memory element; and a plurality of bins distributed in the plurality of frames. Each of the bins includes a logical element. The functional units perform operations relating to Variables stored in the bins, each of the Variables including one or more words.

Processor with frames/bins structure in local high speed memory

A computing device includes a memory structure storing one or more Variables; and a logical mentor. The logical mentor is assigned to at least one of the one or more Variables and performs addressing operations with respect to the Variables to which it is assigned. In an embodiment, a method of computing includes storing one or more Variables in the memory of a computing device, assigning a logical mentor to the Variables; and performing, by the logical mentor, addressing operations with respect to the Variables.

Processor with logical mentor

A computing device with multi-layer control: mentor layer and instruction/control layer includes a memory and one or more functional units. The computing device is configured to implement a multi-layer control structure including a data structure layer including a local high speed memory, a mentor layer, and an instruction/control layer. The local high speed memory includes one or more variables. The mentor layer includes one or more mentor circuits. The mentor circuits control actions associated with the Variables in the local high speed memory. The instruction/control layer includes one or more control circuits that interpret instructions or control operations by one or more functional units. In some embodiments, the local high speed memory implements a frame/bins structure. In some embodiments plural information is included in HLL and/or machine language.

Computing device with frames/bins structure, mentor layer and plural operand processing

A computing device includes a memory storing one or more Variables, and information relating to the singular/plural nature of at least one variable and/or algorithm, one or more functional units (Language Unit). The functional units receive the singular/plural information and perform one or more operations using at least one of the Variables using the singular/plural information. In an embodiment, a method of computing with plural information includes storing, in a memory, one or more Variables, storing, in a memory, information relating to the singular/plural nature of at least one algorithm; receiving at least a portion of the singular/plural information; and performing, using the singular/plural information, one or more operations using at least one of the Variables. In one embodiment, a method of computing includes linguistically implementing, by one or more circuits, plural-form instructions comprising one or more threads. Each thread may be a set of one or more programs. Each thread may be associated with one or more Variables such that the thread can be assigned plural and robustness properties relating to its interaction discipline(s) with other threads.

Processor that uses plural form information

Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided. The combinations have a multiplicity of applications, including combinatorial chemistry, isolation and purification of target macromolecules, capture and detection of macromolecules for analytical purposes, selective removal of contaminants, enzymatic catalysis, cell sorting, sensors and drug delivery, chemical modification and other uses. Methods for tagging molecules, biological particles and matrix support materials, immunoassays, receptor binding assays, scintillation proximity assays, non-radioactive proximity assays, and other methods are also provided. Sensors containing a memory in combination with a matrix are also provided.

Matrices with memories

Automated drug discovery protocols, or partially automated protocols, in which matrices with memories serve as the platform on which all manipulations are performed or serve as the repository of information that is transferred to other memories as the synthesized compounds are processed and screened. Also provided are automated drug discovery units for use in the protocols. The units provide a means for seamless data tracking and include instrumentation and vials with memories for information transfer to other memories in a unit. The units, which are provided herein, include some or all of the following: an automated or manual sorter, microvessels, which contain memories, an automated or semi-automated synthesizer, a microvessel washer/dryer, a manual or automated cleaver for removing compounds from the matrix with memory microvessels, and associated software. The memories may be any of any type, including electromagnetically encodable memories and optical memories, or combinations thereof. The memories may be pre-encoded or may be encodabie during, after or before processing. Also provided are manual and automated methods for sorting matrices with memories.

Automated sorting system for matrices with memory

Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided. The combinations have a multiplicity of applications, including combinatorial chemistry, isolation and purification of target macromolecules, capture and detection of macromolecules for analytical purposes, selective removal of contaminants, enzymatic catalysis, cell sorting, drug delivery, chemical modification and other uses. Methods for tagging molecules, biological particles and matrix support materials, immunoassays, receptor binding assays, scintillation proximity assays, non-radioactive proximity assays, and other methods are also provided.

Growing community of inventors

Austin, TX, United States of America

Hanan Potash