Applied Micro Circuits Corporation

Qualcomm Incorporated

Conexant Systems, Inc.

Hanan Cohen

Simon Pang

Eskinder Hailu

Bupesh Pandita

Li Hsiang Sun

Zhiqin Chen

Kenneth Arcudia

Sudhaker Reddy Anumula

A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.

Compact phase interpolator

An apparatus configured to apply equalization to an input data signal and detect data based on the equalized data signal. The apparatus includes a passive equalizer comprising a first signal path configured to generate a first signal based on an input signal, and a second signal path configured to generate a second signal by filtering the input signal. The apparatus further includes a sense amplifier having an input circuit configured to generate a third signal related to a combination of the first and second signals, and a data detection circuit configured to generate data based on the third signal. The data detection circuit may be configured as a strong-arm latch. The third signal may be a differential current signal including positive and negative current components. The strong-arm latch generating data based on whether the positive current component is greater than the negative current component.

Apparatus and method for combining currents from passive equalizer in sense amplifier

In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.

Fractional phase locked loop (PLL) architecture

Systems and methods for converting digital signals into clock phases are disclosed. An example digital-to-phase converter circuit receives a complementary in-phase and quadrature clock signals and produces four clock outputs at a phase controlled by a digital phase control input. The digital-to-phase converter uses first and second pre-driver modules to buffer the -phase and quadrature clock signals and produce corresponding buffered clock signals having controlled slew rates. Mixer modules produce the clock outputs by forming weighted combinations of the buffered clock signals. The weighting is determined based on the phase control input. The controlled slew rates of the buffered clock signals allow digital mixer module to provide accurate phase control. The digital-to-phase converter may also include an output buffer that compensates for nonlinearities in the relationship between the phases of the clock outputs and the phase control input.

Digital-to-phase converter

A communications system comprising a communications media. A receiver coupled to the communications media and configured to receive a data signal from the communications media. An adaptive equalizer configured to process the data signal and to adjust a multi-frequency inverse transfer function to compensate for a multi-frequency transfer function of the communications media.

Adaptive equalizer utilizing eye diagram

A method is provided for process, voltage, temperature (PVT) stable transfer function calibration in a differential amplifier. The gain resistors of a differential amplifier are initially selected to achieve a flat amplitude transfer function in the first frequency band. After calibration, the degeneration capacitor is connected and tuned until a peaked amplitude transfer function is measured, which is resistant to variations in PVT. As an alternative, the degeneration capacitor is not disconnected during initial calibration. Then, the gain resistors and the degeneration capacitor values are selectively adjusted until the first peaked amplitude transfer function is obtained. The peaked amplitude transfer function remains even more stable to variations in PVT than the flat amplitude calibration method.

System and method for process, voltage, temperature (PVT) stable differential amplifier transfer function

A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).

Frequency integrator with digital phase error message for phase-locked loop applications

A system and method are provided for frequency lock detection using a digital phase error. A lock detection module accepts a digital phase error (pherr) message proportional to an error in phase between a reference clock and a (synthesizer clock*Nf). Also accepted is a unitless frequency error tolerance value (&#x394;f). The lock detection module periodically supplies a lock detect signal, indicating whether the synthesizer clock frequency is within the frequency error tolerance value of the reference clock frequency.

Lock detection using a digital phase error message

A successive time-to-digital converter (STDC) method is provided for supplying a digital word representing the ratio between a phase-locked loop PLL frequency synthesizer signal and a reference clock. The number of frequency synthesizer clock cycles per reference clock cycle is counted. A first difference is measured between a reference clock period and a corresponding frequency synthesizer clock period. In response to the first measurement, a second difference is measured between a delayed reference clock period and the corresponding frequency synthesizer clock period, where the second difference is less than the first difference. A third difference is measured as a time duration between the delayed reference clock period and the corresponding delayed frequency synthesizer clock period. The first and third difference measurements and the count of the number of frequency synthesizer clock cycles per reference clock cycle are used to calculate a digital error signal supplied to the frequency synthesizer.

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San Diego, CA, United States of America

Hanan Cohen