International Business Machines Corporation

Hanafy E Meleis

Dominick Anthony Zumbo

Gary Scott Delp

Paul S Chang

David Israel Seidman

Ahmed N Tantawy

Rafael M Montalvo

Mon-Song Chen

Barry C Goldstein

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. A packet memory stores data packets arriving at a plurality of generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. The generic adapter manager prepares future response to anticipated requests for communications services which are functions of the current requests for communication services, such as preparing a response for an anticipated request for a next buffer by a current request for a receipt of data. The generic adapter manager stores the future responses at specified addresses in memory which can be read by a requester. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

Generic high bandwidth adapter providing data communications between

A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.

Generic high bandwidth adapter having data packet memory configured in

A communication system provides high speed transmission of data over a link, such as a fiber optic link, between a first terminal and a second terminal. The architecture and protocol permits the use of dedicated hardware such as state machines constructed of programmable array logic units, to synchronize the transmission and reception of data packets and the retransmission of designated ones of these packets in the event of a faulty transmission. Packets to be transmitted and received are stored in an array of frames in sub-windows of a memory storage window in each of the termianls, the frame number being equal to the sequence number of the data packet. By embedding sequence and status bits in each packet within control words and bits appended to each packet, the state machine in each terminal can readily track the progress of each packet so as to request acknowledgement of error-free receipt, to send an acknowledgement, to request a retransmission of a packet designated by its serial number and to distinguish a retransmitted packet from an original packet transmitted with error.

Adaptive data link protocol

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Yorktown Heights, NY, United States of America

Hanafy E Meleis