Kioxia Corporation

Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Hanae Ishihara

Go Oike

Wataru Sakamoto

Hiroshi Nakaki

Toru Matsuda

Kaito Shirai

Masaru Kito

Mitsuru Sato

Mitsuhiro Noguchi

Shigeki Kobayashi

Daigo Ichinose

Yumiko Miyano

Shingo Nakajima

Kojiro Shimizu

Ryosuke Sawabe

A semiconductor device of the embodiment includes a stacked body, a first insulating layer, first and second staircase portionsand a second insulating layerThe stacked body includes a first electrode layer(WLDD) and a second electrode layer(SGD). The first and second staircase portionsare provided in a first end portiona second end regionThe second insulating layerextends in the X-direction. The second insulating layer divides the second electrode layer(SGD) in the X-direction direction. A length Lin the X-direction of the second insulating layeris longer than a length Lin the x-direction of the second electrode layer(SGD) and shorter than a length Lin the X-direction of the first electrode layer(WLDD).

Semiconductor device for preventing an increase in resistance difference of an electrode layer

A device includes a first region including first semiconductor pillars extending through first conductive layers; a second region including second semiconductor pillars extending through second conductive layers; and a third region disposed between the first region and the second region and including insulator columns extending through third conductive layers. The third region includes a fourth region and a fifth region. In the fourth region, one third conductive layer electrically connects one first conductive layer and one second conductive layer to each other, and in the fifth region, one third conductive layer is connected to a contact plug. A first diameter of a first subset of the insulator columns provided in the fourth region is smaller than a second diameter of a second subset of the insulator columns provided in the fifth region.

Semiconductor storage device

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of first members, and at least one first insulating member. The stacked body is provided on the substrate and includes a plurality of electrode layers. The electrode layers are stacked apart from each other in a first direction and extend in a second direction parallel to an upper surface of the substrate. The first members are provided in the stacked body and extend in the first direction and the second direction. The first insulating member is provided in the stacked body and extends in the first direction and a third direction so that the electrode layers are divided into a plurality of regions in the second direction, the third direction intersecting with the second direction and being parallel to the upper surface of the substrate.

Semiconductor memory device

A semiconductor memory device includes a semiconductor substrate, a memory cell array, and first and second wirings. The semiconductor substrate includes first region to third region and fourth region to sixth region. The memory cell array includes first conducting layers extending in a second direction from the first region to the third region and laminated in a first direction, first and second semiconductor layers disposed in the first and third regions, extending in the first direction, and opposed to the first conducting layers, first and second contacts disposed in the fourth and sixth regions and extending in the first direction, and a third semiconductor layer disposed in the fifth region and extending in the first direction. The first wiring is connected to the first semiconductor layer and the second contact. The second wiring is connected to the second semiconductor layer and the third contact.

A semiconductor storage device includes a memory cell array including a stacked body having insulating layers and conductive layers that are alternately stacked. The memory cell array includes a cell area and a contact area provided adjacent the cell area. The semiconductor storage device includes: a circuit below the memory cell array; a source layer between the memory cell array and the circuit; a first contact in the contact area, and coupled to the circuit; a second contact over the cell area and the contact area; a first wiring extending in a direction intersecting an extending direction of the second contact in the contact area; a second wiring above the second contact, extending along the second contact in the contact area, and connected to the first wiring; and third contacts between the second wiring and the second contact.

Semiconductor storage device with contact melting prevention

A memory device includes a substrate, first, second, and third conductive layers, a stack of fourth conductive layers, a memory pillar, and an insulator. The first, second, and third conductive layer are provided above the substrate. The stack of fourth conductive layers is provided above the third conductive layer. The memory pillar extends in the thickness direction through the stack and the third conductive layer and into the second conductive layer in a first region of the memory device. The insulator extends in a thickness direction through the stack, the third conductive layer, and the second conductive layer in a second region of the memory device. The insulator also extends in a second surface direction of the substrate. A thickness of the third conductive layer in a region through which the insulator extends is greater than a thickness of the third conductive layer in the first region.

Memory device

The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.

Memory device and manufacturing methods thereof

A semiconductor device according to an embodiment includes a first contact electrically connected to a first conductive layer with a diameter size smaller than a diameter size of a first support pillar at a region position on an inner side in a radial direction of the first support pillar in a first region and extending to the opposite side of the substrate with respect to the first conductive layer; and a second contact electrically connected to a second conductive layer with a diameter size smaller than a diameter size of a second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer.

Semiconductor device

A storage device includes a first wiring layer, a second wiring layer spaced from the first wiring layer in a first direction, and a plurality of electrode layers stacked in the first direction between the first wiring layer and the second wiring layer. A semiconductor pillar penetrates the plurality of electrode layers in the first direction. The plurality of electrode layers includes a first electrode layer connected to a first wire in the first wiring layer and a second electrode layer connected to a second wire in the second wiring layer.

Storage device including multiple wiring and electrode layers

A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.

Growing community of inventors

Yokkaichi, Japan

Hanae Ishihara