Micron Technology Incorporated

Qualcomm Incorporated

Intel Corporation

The University of Texas System

Apple Inc.

Lodestar Licensing Group LLC

Han Zhao

Toru Tanzawa

Krishna Kumar Parat

Haitao Liu

Koji Sakui

Akira Goda

Pranav Kalavade

Shigekazu Yamada

Gheorghe Calin Cascaval

Arun Raman

Aurelio Giancarlo Mauri

Aravind Natarajan

Tushar Kumar

Dario Suarez Gracia

Han Liu

Violante Moschiano

Shantanu R Rajwade

Andrea D'Alessandro

Purval Shyam Sule

Jack C Lee

Pablo Montesinos Ortego

Fatma Arzum Simsek-Ege

Baris Cagdaser

Guangyu Huang

Jie Sun

Srikant Jayanti

John T Wetherell

Benben Li

Behnam Robatmili

Omar Hafiz

Richard M Fastow

James Xenidis

Narayanan Ramanan

Wenjia Ruan

Shaizeen Aga

Arun Thathachary

Dario Suárez Gracia

Ravish Hastantram

Aurielo Giancarlo Mauri

Andrea D'alessandro

Purval S Sule

Shantanu Rajwade

Jie Jason Sun

Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.

Configuration of a memory device for programming memory cells

In an embodiment, an electronic display includes an active area including a plurality of pixels arranged in columns and a plurality of source drivers driving image data to columns of pixels. The electronic display also includes a first plurality of switches selectively coupling respective source drivers of the plurality of source drivers to one or more columns. Selective coupling enables the respective source drivers to, at different times, drive the image data to: a single column; and multiple columns. In another embodiment, an electronic display includes a display panel configured to operate using a reference voltage received via a resistive path having a routing resistance, a reference voltage source outputting the reference voltage, and a feedback circuit sensing an electrical parameter of the resistive path and producing a compensation voltage that, when added to the reference voltage, causes the reference voltage to remain substantially constant at the display panel.

Foveated driving for power saving

Reduction of program disturb degradation in a flash memory cell array is facilitated by selectively switching wordline voltage levels in a sequence that reduces the likelihood of trapping electrons in memory cell channels. During a program verify operation for a memory cell in a memory cell string, a flash memory system switches wordline voltage levels from high-to-low for interface wordlines, prior to switching wordline voltages from high-to-low for other wordlines in a memory cell string. Selectively switching wordlines in a sequence in the memory cell string enables electrons to migrate to ground or to a source voltage through upper and lower select gates.

Method and system for reducing program disturb degradation in flash memory

Methods of operating a memory include activating a respective memory cell of each string of series-connected memory cells of a plurality of strings of series-connected memory cells, selectively activating a target memory cell of a selected string of series-connected memory cells of the plurality of strings of series-connected memory cells depending upon its data state, and deactivating a respective memory cell of each string of series-connected memory cells of a first subset of the plurality of strings of series-connected memory cells.

Segmented memory operation

A technique for read or program verify (PV) operations for non-volatile memory is described. In one example, at the end of a program verify operation (e.g., during a program verify recovery phase), a number of wordlines near a selected wordline are ramped down one at a time. Ramping down wordlines near the selected wordline one at a time can significantly reduce the trapped charge in the channel, enabling lower program disturb rates and improved threshold voltage distributions. In one example, the same technique of ramping down wordlines near the selected wordline can be applied to a read operation.

Program verify technique for non-volatile memory

Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

Apparatuses and methods to control body potential in 3D non-volatile memory operations

Memories having a controller configured to perform methods during programming operations including applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

Apparatus having a plurality of strings of series-connected memory cells, and methods of their operation, where each string of series-connected memory cells of the plurality of strings of series-connected memory cells may be selectively connected to a common data line through a corresponding respective select gate, a first set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a second set of access lines may each be coupled to a respective memory cell of each string of series-connected memory cells of only a portion of the plurality of strings of series-connected memory cells.

Segmented memory and operation

Methods include applying a first voltage level to first and second data lines while applying a second, lower, voltage level to first and second select gates connected between the data lines and respective strings of memory cells; decreasing a voltage level of the first data line to a third voltage level; increasing a voltage level of the first select gate to a fourth voltage level; applying a fifth voltage level, higher than the first voltage level, to first and second access lines coupled to memory cells of the strings of memory cells; and increasing a voltage level of the first access line to a sixth voltage level.

Operation of a memory device during programming

Various embodiments proactively balance workloads between a plurality of processing units of a multi-processor computing device by making work-stealing determinations based on operating state data. An embodiment method includes obtaining static characteristics data associated with each of a victim processor and one or more of a plurality of processing units that are ready to steal work items from the victim processor (work-ready processors), obtaining dynamic characteristics data for each of the processors, calculating priority values for each of the processors based on the obtained data, and transferring a number of work items assigned to the victim processor to a winning work-ready processor based on the calculated priority values. In some embodiments, the method may include acquiring control over a probabilistic lock for a shared data structure and updating the shared data structure to indicate the number of work items transferred to the winning work-ready processor.

Proactive resource management for parallel work-stealing processing systems

A vertical-mode tunnel field-effect transistor (TFET) is provided with an oxide region that may be laterally positioned relative to a source region. The oxide region operates to reduce a tunneling effect in a tunnel region underlying a drain region, during an OFF-state of the TFET. The reduction in tunneling effect results in a reduction or elimination of a flow of OFF-state leakage current between the source region and the drain region. The TFET may have components made from group III-V compound materials.

Tunnel field-effect transistor (TFET) with lateral oxidation

Growing community of inventors

Santa Clara, CA, United States of America

Han Zhao