Synopsys, Inc.

Ansys, Inc.

Han Young Koh

Jeh-Fu Tuan

Tak K Young

Li Ding

Kayhan Kucukcakar

Ahmed M Shebaita

Chiping Ju

Hurley H Song

Systems, machine readable media and methods are described for analyzing one or more physical systems using techniques that recognize patterns in underlying data and use the patterns to efficiently compute outputs using the patterns to reduce computations. The physical systems can be simulated with an estimation (e.g., an estimated power versus time waveform) that can be efficiently computed and then the estimation can be analyzed to detect patterns in the data. The detected patterns can each be analyzed with, in one embodiment, higher accuracy than the estimation to provide data that can be combined across multiple instances of each pattern to provide a higher accuracy evaluation of the system with a lower computational overhead.

Time-based power analysis

Techniques and systems for determining an output waveform at an output of a complementary metal-oxide-semiconductor (CMOS) logic gate are described. Some embodiments can identify at least one set of inputs of the CMOS logic gate that, when switched together, causes multiple transistors coupled in parallel to simultaneously turn-on and drive the output of the CMOS logic gate. Next, the embodiments can determine a set of current source models that are coupled in parallel to model the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together. The embodiments can then simulate the set of current source models together to determine the output waveform at the output of the CMOS logic gate when the set of inputs of the CMOS logic gate are switched together.

Accurately calculating multi-input switching delay of complemantary-metal-oxide semiconductor gates

A unique, efficient method and system for reliability simulation of a semiconductor chip design comprising millions of transistors. Specifically, the instant method starts by storing device information about a chip design as inputted. Next, by first partitioning the complex circuit of the design into numerous smaller stages, each of which confines direct current flow within its boundary, then estimating the current consumption and the relative current contribution of each transistor for each stage, the method of the present invention determines the individual currents of all power network transistors with sufficient accuracy for reliability simulation. The instant method then uses the individual transistor currents and the stored device information, including data of an accurate resistor-capacitor model of the power network, to determine the branch currents and node voltages in all interconnect wires of the power network. Finally, the instant method reports all potential problems of the design identified based on the values of the branch currents and node voltages. As such, the present invention enables circuit designers to pinpoint where voltage drop and electro-migration may pose problems and take appropriate corrective actions before chips are fabricated and sold. Thus, the present invention provides a novel and superior method for reliability simulation over the prior art by offering much greater simulation speed and capacity over conventional reliability simulation tools while delivering highly accurate results for reliability analysis crucial to today's deep sub-micron CMOS designs.

Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities

A method for testing for power supply network voltage drop violations in an integrated circuit through a computer simulation. First, the IC chip area is divided into a number of discrete regions. The simulation time is divided into a number of time segments. Next, the average aggregate currents corresponding to the transistors for each of the regions are calculated for each of the time segments. Only when a peak average current occurs for any one of the plurality of regions is the power supply network of the IC chip simulated for that time segment. Based on the voltage drops as determined by the power network simulation, violation conditions can be easily identified. Thus, the power network of the IC chip is simulated only when there is found to be high switching activity in some region of the chip. This is more efficient than performing power network voltage drop analyses all the time, even when switching activity throughout the chip is low and the likelihood of any voltage drop violations is very low.

Method and system of performing voltage drop analysis for power supply

The present invention pertains to a method for analyzing a semiconductor chip design for determining potential voltage drop and electromigration problems. Initially, the semiconductor chip design is divided into a plurality of blocks. A block level verification is then performed based on the assumption that full voltage is being supplied to each of the blocks. Next, the blocks are modeled by an equivalent RC network. This RC network is then reduced into a simpler representation. The voltage drops are determined based on the reduced, equivalent model. The blocks are then reanalyzed with the supply voltage input to the blocks reduced according to the calculated voltage drops. Thereby, a more realistic simulation can be achieved.

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Fremont, CA, United States of America

Han Young Koh