Sun Microsystems, Inc.

Han Y Ko

Drew George Doblar

Ashok Singhal

Michael C Freda

Ali Hassanzadeh

Robert Calvin Cyphers

Alan Dean Martin

Clement Fang

Tayung Wong

William L Robertson

John Carrillo

Stephen K Gee

Deepak Rao

Keith Y Oka

Tomonori Hirai

A method for configuring a circuit for providing a power OK (POK) signal is described. The method includes identifying a voltage range and voltage interval, dividing the voltage range into a plurality of segments, selecting a reference voltage for each segment, and selecting resistor values for a plurality of voltage dividers for dividing an output voltage from a precision voltage reference into each of the reference voltages. A power OK signal generator and method for generating a power OK signal are also described.

Accurate hardware Power OK (POK) generation methodology for processors with varying core voltage requirements

An electrical connector for conveying signals between two circuit boards includes a first connector portion including a first array of board contacts for connection to a first corresponding footprint on a first circuit board. The connector also includes a second connector portion including a second array of board contacts for connection to a second corresponding footprint on a second circuit board. The signals include a plurality of signal groups each including a different plurality of related signals. Each of the signal groups is assigned to a grouping of related board contacts of the first array and to a corresponding grouping of related board contacts of the second array. When the first connector portion and the second connector portion are mated, each grouping of board contacts of the first array is electrically coupled to the corresponding grouping of board contacts in a transposed location in the second array.

Electrical connector for conveying signals between two circuit boards

A system and method for providing a common power detect and presence detect signal. In one embodiment, a memory module includes a voltage regulator and a power detector circuit. The voltage regulator may be configured to provide a stable operating voltage to the various circuits of the memory module. The power detector circuit may be configured to detect the presence of the operating voltage from the output of the voltage regulator. The power detector circuit may assert an output signal in response to a detection of a voltage from the voltage regulator. The output signal asserted by the power detector circuit may then be driven through a single pin of a connector mounted to the memory module to a storage unit of the host computer system. The storage unit may be configured to store the state of the output signal. Instructions executed by a central processing unit (CPU) of the computer system may cause the state of the output signal to be periodically read from the storage unit, and provide an indication as to whether the voltage regulator is providing the operating voltage. If the memory module is not receiving the correct operating voltage, or it is not present, an indication of this condition may be provided to a user of the computer system.

Method and system for using a combined power detect and presence detect signal to determine if a memory module is connected and receiving power

A memory module comprising a printed circuit board having mounting locations for a plurality of memory chips. A line driver having a plurality of outputs for each input is used to drive address and control signals to the chips, with each set of outputs coupled to a subset of the chips. Memory access time is improved by limiting subset size and thereby limiting driver loading. Subsets may correlate to banks of memory chips. Access time is substantially the same for a module with a plurality of banks of memory chips as it is for a module with only one bank of chips. Computer memory may be efficiently exchanged by using only such memory modules, allowing higher clock speed since the range of memory access times is reduced and requiring no change to system memory configuration or settings. Memory modules having differing capacities can be easily interchanged in the system.

Memory module with equal driver loading

A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended &ldquo;regenerated&rdquo; clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit. Each of the multiple memory devices is coupled to receive the regenerated clock signal, and the operations of the multiple memory devices are synchronized to the regenerated clock signal. The multiple memory devices within the memory module may be coupled to receive the memory access signals produced by the memory controller, and may store data or retrieve data in response to the memory access signals and the regenerated clock signal. The multiple memory devices may include synchronous dynamic random access memory (SDRAM) devices, and the memory module may be a dual in-line memory module (DIMM).

Computer system providing low skew clock signals to a synchronous memory unit

A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

System and method for improving multi-bit error protection in computer memory systems

An apparatus and system comprising electrical interconnection devices (EIDs), such as printed wiring boards, semiconductor packages, and printed circuit boards, having novel via and signal trace positioning. The vias may be positioned off-center from the pattern of the surface pads. Via groups, or staircase vias, connect surface pads with vias extending into the electrical interconnection device. The via groups convert the pad geometry on the surface to a more open via pattern on one or more internal layers. The EID comprises a plurality of pads formed on a surface for providing electrical connections to another EID. A plurality of vias each extend from a corresponding pad to another layer of the printed wiring board. Each via is offset from a central location of its corresponding pad. A via group comprises a plurality of vias with a first via connecting a surface of the electrical interconnection device to a first inner layer electrically connects a pad on a surface of the electrical interconnection device to a second via. The second via extends from the first inner layer to a second layer of the electrical interconnection device. The centers of the first via and the second via are non-collinear. Another EID includes a uniformly spaced set of pads on the surface. Via groups, comprising a first set of vias and a second set of vias, extend from the uniformly spaced surface pads. Spacing among the second set of vias is non-uniform.

Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging

An apparatus for suppressing power bus bouncing in a hot-swappable system has been developed. The apparatus includes a connection module with three interior pins for: the power return; the power supply; and the system ground. The system ground pin is shorter than the other two so that it makes contact with the power bus after the bouncing from the return and supply pins has subsided.

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San Jose, CA, United States of America

Han Y Ko