Intel Corporation

Google Inc.

Tahoe Research, Ltd.

Han Wui Then

Marko Radosavljevic

Sansaptak W Dasgupta

Robert S Chau

Paul B Fischer

Ravi Pillarisetty

Seung Hoon Sung

Benjamin Chu-Kung

Sanaz Kabehie Gardner

Niloy Mukherjee

Walid M Hafez

Gilbert W Dewey

Jack T Kavalieros

Willy Rachmady

Van H Le

Matthew V Metz

Rahul Ramaswamy

Nidhi Nidhi

Johann Christian Rode

Valluri Ramana Rao

Bruce A Block

Niti Goel

Johanna M Swan

Adel A Elsherbini

Jessica S Kachian

Shawna M Liff

Kevin Lai Lin

Harald Gossner

Kimin Jun

Nicole K Thomas

Peter Baumgartner

Stephan Leuschner

Richard Geiger

Uday Shah

Domagoj Siprak

Nancy M Zelick

Uwe Hodel

Sherry R Taft

Pratik Koirala

Aleksandar Aleksov

Feras Eid

Glenn A Glass

Scott Bruce Clendenning

Peter G Tolchinsky

Mohammad Enamul Kabir

Brian S Doyle

Anand S Murthy

Patrick R Morrow

Charles C Kuo

Gerhard Schrom

Roza Kotlyar

Krishna Bharath

Gerald S Pasdast

Ibrahim Ban

Beomseok Choi

Kevin P O'brien

Samuel James Bader

Nityan Labros Nair

Sandrine Charue-Bakker

Seung Hoon Hoon Sung

Samuel Jack Beach

Pavel M Agababov

Abhishek A Sharma

Prashant Majhi

Zhiguo Qian

Zdravko Boos

Wilfred Gomes

Mark Armstrong

Satyarth Suri

Tristan A Tronic

John J Plombon

Michael L McSwiney

Gregory W Chance

Robert B Turkot, Jr

Dipanjan Basu

Nebil Tanzi

Yang Cao

Georgios Panagopoulos

Robert Ehlert

Nicholas James Harold McKubre

Sanaz Kabehie

Luis Giles

Rajat K Paul

Marko Radosavlijevic

Nicholas McKubre

Tushar Talukdar

Mark Radosavljevic

Benjamin Chu-King

Nitika Goel

Sansaptak Dusgupta

Heli Chetanbhai Vora

Xiaojun Weng

Co-integrated gallium nitride (GaN) complementary metal oxide semiconductor (CMOS) integrated circuit technology is described. In an example, a semiconductor structure includes a silicon (111) substrate having a first region and a second region. A structure including gallium and nitrogen is on the first region of the silicon (111) substrate, the structure including gallium and nitrogen having a top surface. A structure including germanium is on the second region of the silicon (111) substrate, the structure including germanium having a top surface co-planar with the top surface of the structure including gallium and nitrogen. A dielectric spacer is laterally between and in contact with the structure including gallium and nitrogen and the structure including germanium, the dielectric spacer on the silicon (111) substrate.

Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology

Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

Transistor gate trench engineering to decrease capacitance and resistance

Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.

Contiguous shield structures in microelectronic assemblies having hybrid bonding

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.

Microelectronic assemblies having backside die-to-package interconnects

Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

III-N diodes with n-doped wells and capping layers

High voltage metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.

High voltage metal insulator metal (MIM) capacitor

Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

Gallium nitride (GaN) integrated circuit technology

An integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width and a first height. A second trench is in the substrate, the second trench having a second width and a second height. The second width is greater than the first width, and the second height is greater than the first height. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate.

Gallium nitride (GaN) selective epitaxial windows for integrated circuit technology

Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.

Gallium nitride (GaN) integrated circuit technology with optical communication

Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

Direct bonding in microelectronic assemblies

Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.

Inductor/core assemblies for integrated circuits

Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

Gallium nitride (GAN) three-dimensional integrated circuit technology

Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.

Integration of Si-based transistors with non-Si technologies by semiconductor regrowth over an insulator material

Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances

A device including a III-N material is described. In an example, the device has terminal structure having a first group III-Nitride (III-N) material. The terminal structure has a central body and a first plurality of fins, and a second plurality of fins, opposite the first plurality of fins. A polarization charge inducing layer is above a first portion of the central body. A gate electrode is above the polarization charge inducing layer. The device further includes a source structure and a drain structure, each including impurity dopants, on opposite sides of the gate electrode and on the plurality of fins, and a source contact on the source structure and a drain contact on the drain structure.

Group III-nitride (III-N) devices with reduced contact resistance and their methods of fabrication

Growing community of inventors

Portland, OR, United States of America

Han Wui Then