Skhynix Inc.

Han Woo Cho

Hyo Seob Yoon

Gyu Hyun Kim

Hyun Min Lee

Byoung Ki Lee

An electronic device includes a semiconductor memory comprising row lines, column lines, memory cells, and a plurality of contact plugs including row contact plugs respectively coupled to the row lines and column contact plugs respectively coupled to the column lines. Each memory cell is coupled to a row line and a column line, and has a current path comprising a portion of that row line and a portion of that column line. First and second contact plug are respectively coupled to first and second memory cells respectively having first and second current paths. A resistance of the first current path is lower than a resistance of the second current path, and a resistance of the first contact plug is increased relative to a resistance of the second contact plug to offset the lower resistance of the first current path.

Electronic device and method of fabricating the same

A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.

Semiconductor device including an etching stop layer and method of manufacturing the same

Semiconductor device including a resistive memory layer and method of manufacturing the same including the cleaning of byproducts

A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device includes a first insulating layer formed on a semiconductor substrate, the first insulating layer having a first hole formed therein. A switching device is formed in the first hole. A second insulating layer is formed over the first insulating layer and the second insulating layer includes a second hole. A lower electrode is formed along a surface of the second insulating layer that defines the second hole. A spacer is formed on the lower electrode and exposes a portion of the surface of the lower electrode. A variable resistance material layer is formed in the second hole, and an upper electrode is formed on the variable resistance material layer.

Variable resistance memory device

Variable resistance memory device and method of manufacturing the same

A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.

Resistive memory device and fabrication method thereof

A resistive memory device and a method for manufacturing the same are provided. The resistive memory device includes a lower electrode, a variable resistive layer formed on the lower electrode and configured so that the volume thereof is contracted or expanded according to temperature, and an upper electrode formed on the variable resistive layer. At least a portion of the lower electrode is configured to be electrically connected to the upper electrode.

Growing community of inventors

Gyeonggi-do, South Korea

Han Woo Cho