Taiwan Semiconductor Manufacturing Comp. Ltd.

Han-Wen Liao

Chih-Yu Lin

Chun-Chih Lin

Cherng-Chang Tsuei

Hong-Ting Lu

Yen-Yu Chen

Jun-Xiu Liu

Shih Wei Bih

Chung-Hsi Wu

Xuan-You Yan

Hsu-Shui Liu

Chen-Hsiang Lu

Chun-Jung Huang

Jun Xiu Liu

Yung-Lin Hsu

Kuang-Huan Hsu

Wen-Sheng Wang

Yu-Yao Huang

Wei-Tai Lin

Hsiao-Wei Chen

A wet etch apparatus includes a wafer chuck, a dispensing nozzle above the wafer chuck, a rail, first and second vehicles, and an electric field generator. The rail extends at least from a first position aligned laterally with the wafer chuck to a second position higher than a top surface of the wafer chuck. The first and second vehicles are movable along the rail. The electric field generator is operative to generate an electric field across the wafer chuck. The electric field generator comprises a first electrode carried by the first vehicle and a second electrode carried by the second vehicle.

Wet etch apparatus

A wet etch apparatus includes a wafer chuck, a dispensing nozzle, a liquid etchant container, and an electric field generator. The dispensing nozzle is above the wafer chuck. The liquid etchant container is in fluid communication with the dispensing nozzle. The electric field generator is operative to generate an electric field across the wafer chuck. The electric field generator includes a first electrode and a second electrode spaced apart from the first electrode in a direction substantially perpendicular to a top surface of the wafer chuck, and the second electrode is an electrode plate above the wafer chuck.

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode

A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.

Semiconductor structure and planarization method thereof

A plasma-processing apparatus includes a chamber, a plasma generator, and a composite plasma modulator. The chamber includes a plasma zone. The plasma generator is configured to generate a plasma in the plasma zone. The composite plasma modulator is configured to modulate the plasma. The composite plasma modulator includes a dielectric plate made of a first dielectric material and a first modulating portion made of a second dielectric material and coupled to the dielectric plate.

Composite plasma modulator for plasma chamber

Methods for enhancing a surface topography of a structure formed on a substrate are provided. In one example, the method includes performing a polishing process on a substrate having a shallow trench isolation structure and a diffusion region, performing a surface topography enhancing process to enlarge a defect in at least one of the shallow trench isolation structure and the diffusion region, inspecting at least one of the shallow trench isolation structure and the diffusion region to detect the enlarged defect, and adjusting a parameter of the polishing process in response to detecting the enlarged defect.

Methods of enhancing surface topography on a substrate for inspection

A method includes dispensing a chemical solution including charged ions onto a semiconductor substrate to chemically etch a target structure on the semiconductor substrate, and applying an electric field on the semiconductor substrate during dispensing the chemical solution on the semiconductor substrate, such that the charged ions in the chemical solution are moved in response to the electric field.

Wet etch apparatus and method of using the same

A method for manufacturing a semiconductor device includes forming a semiconductor fin over a substrate. A fin spacer is formed on a sidewall of the semiconductor fin. An e-beam treatment is performed on the fin spacer. An epitaxial structure is formed over the semiconductor fin. The epitaxial structure is in contact with the e-beam treated fin spacer.

Semiconductor device and manufacturing method thereof

A method for manufacturing a semiconductor structure includes depositing a wafer in a processing chamber. Plasma is formed in the processing chamber to process the wafer. A plasma concentration over a peripheral region of the wafer is detected. A plasma distribution over the peripheral region of the wafer is adjusted according to the detected plasma concentration.

Plasma processing apparatus and manufacturing method using the same

A cluster tool includes a polyhedral transfer chamber, at least one processing chamber, at least one load lock chamber, and an electron beam (e-beam) source. The processing chamber is connected to the polyhedral transfer chamber. The processing chamber is configured to perform a manufacturing procedure to a wafer present therein. The load lock chamber is connected to the polyhedral transfer chamber. The e-beam source is configured to performing an e-beam treatment to the wafer after the wafer is performed the manufacturing procedure.

Cluster tool and manufacuturing method of semiconductor structure using the same

A method includes dispensing a liquid etchant onto a wafer, wherein the wafer is free from rotation during dispensing the liquid etchant; blowing the liquid etchant on the wafer using a gas flow, wherein a direction of the gas flow remains substantially constant during dispensing the liquid etchant; and turning the gas flow off after a target structure on the wafer is etched away by the liquid etchant.

Wet etch apparatus and method for using the same

A system is configured to perform plasma related fabrication processes. The system includes a process chamber and a wafer stage positioned within the process chamber. The wafer stage is configured to secure a process wafer. The system further includes a bottom electrode positioned beneath the wafer stage, a top electrode positioned external to the chamber, and a plasma distribution mechanism. The plasma distribution mechanism is reconfigurable to allow for more than one plasma distribution profile.

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Taichung, Taiwan

Han-Wen Liao