Taiwan Semiconductor Manufacturing Comp. Ltd.

Han-Wei Wu

Jin-Dah Chen

Ming-Feng Shieh

Hua-Tai Lin

Stan Chen

Po-Chun Liu

Yu-Hsien Lin

Wei-De Ho

Pei-Sheng Tang

Yuan-Hsiang Lung

Chin-Ta Chen

Feng-Cheng Yang

Hung-Chang Hsieh

Szu-Ping Tung

Meng-Jung Lee

Lan-Hsin Chiang

Jiann-Yuan Huang

Ru-Gun Liu

Meng-Han Lin

Wei-Yang Lee

Shih-Ming Chang

Yung-Sung Yen

Ting-Yeh Chen

Chen-Jung Wang

Chih-Jie Lee

Chiu-Hsiang Chen

Shih-Hsuan Chien

A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Method for evaluating non-uniform stress

In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.

Method of manufacturing semiconductor devices

A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.

Memory device and manufacturing method thereof

A method of manufacturing a semiconductor device includes forming an underlying structure in a first area and a second area over a substrate. A first layer is formed over the underlying structure. The first layer is removed from the second area while protecting the first layer in the first area. A second layer is formed over the first area and the second area, wherein the second layer has a smaller light transparency than the first layer. The second layer is removed from the first area, and first resist pattern is formed over the first layer in the first area and a second resist pattern over the second layer in the second area.

Method of manufacturing a semiconductor device

A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.

Memory structure and method of forming the same

A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.

Gate formation with varying work function layers

Thin-film non-uniform stress evaluation

In a method of patterning an integrated circuit, test layer thickness variation data is received when a test layer with a known thickness disposed over a test substrate undergoes tilted angle plasma etching. Overlay offset data per substrate locations caused by the tilted angle plasma etching is determined. The overlay offset data is determined based on the received thickness variation data. The overlay offset data is associated with an overlay between first circuit patterns of a first layer on the semiconductor substrate and corresponding second circuit patterns of a second layer disposed over the first layer on the substrate. A location of the substrate is adjusted based on the overlay offset data during a lithography operation to pattern a resist layer over the second layer. The second layer is patterned based on the projected layout patterns of the reticle and using the tilted angle plasma etching.

Etch monitoring and performing

First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.

Loading effect reduction through multiple coat-etch processes

A semiconductor component includes a substrate having a dense zone and a less-dense zone, at least one first FinFET device disposed on the dense zone, and at least one second FinFET device disposed on the less-dense zone, in which a width of a first source/drain region of the first FinFET device is smaller than a width of a second source/drain region of the second FinFET device.

Semiconductor component and fabricating method thereof

A lithography system is provided. The lithography system includes a mask and an optical module. The optical module is configured to optically form an invisible pellicle over the mask to protect the mask from contaminant particles. As a solid pellicle used in the prior arts is omitted, the critical dimension (CD) error from the boarder effect due to reflection of some light by the solid pellicle and the exposure radiation energy consumption caused by the solid pellicle can be avoided.

Growing community of inventors

Tainan, Taiwan

Han-Wei Wu