Texas Instruments Corporation

Other

United States of America as Represented by the Secretary of the Air Force

Han-Tzong Yuan

Jau-Yuann Yang

Donald L Plumton

Francis J Morris

Tae S Kim

Hisashi Shichijo

Walter Marvin Duncan

Hung-Dah Shih

Albert H Taddiken

Liem T Tran

William V McLevige

Friedrich H Doerbeck

Taylor R Efland

Simon Joshua Jacobs

Louis N Hutter

Francis Gabriel Celii

Gregory A Magel

Hua Q Tserng

John P Erdeljac

Alan C Seabaugh

Theo J Powell

Shiban Kishan Tiku

Lee R Reid

John Kenneth Arch

Satish M Thatte

Jeffrey P Smith

C Matthew Thompson

Terrance Gus McDonald

Thirumalai Sridhar

Hung Y Yee

David S Ho

Mary Ann Murphy

Roger Norman Anderson

Nancy J Gabriel

Lee R Reid, Deceased

Donald L Plumpton

The invention relates to an improved substrate ( ) using a layer ( ) or region ( ) of porous silicon that is created in the bulk silicon substrate material ( ) to increase the resistivity of the substrate ( ) thus making it suitable for passive component integration directly on the motherboard ( ) or chip ( ) and useful for high frequency applications due to its low loss, low dielectric properties. One or more passive components such as inductors ( ), resistors ( ) and capacitors ( ) can be integrated on the device ( ) over the porous silicon region ( ). The high resistivity of the device makes it ideal for integration on a single platform using conventional wafer fab processes since loss at radio frequencies is comparably less when compared to a pure silicon substrate.

Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications

An optocoupler structure comprising a semiconductor chip having an integrated circuit and an optically transparent, electrically insulating layer having first and second surfaces; an organic diode integral with said first surface, said diode operable to emit electromagnetic radiation; and said circuit including a radiation-sensitive semiconductor device integral with said second surface, electrically isolated from said diode, and positioned in the path of said radiation.

Optocouplers having integrated organic light-emitting diodes

An resonator circuit and an integrated circuit including the resonator circuit and method of making. A silicon substrate of a first conductivity type (,) is provided and an integrated circuit TFR circuit (,) is formed on a region of the substrate which includes a stack containing a plurality of alternately non-porous (,) silicon and porous (,) silicon layers. A method is provided to deposit layers with alternately opposite conductivity type and convert only one conductivity type but not the other into porous silicon materials. Each of these layers generally has the thickness which is one quarter of an acoutic wavelength of the resonator frequency. A noise isolator (,) is disposed along the sidewalls of the stack and extends into the substrate. A region of silicon (,) is disposed on the substrate and separated from the reflector by the noise isolator. At least one of an active and/or passive device (,) is disposed on or in said region of silicon. There can additionally or alternatively be at least one passive device disposed over the noise isolator (,) with an interconnect (,) interconnecting the resonator and the at least one of an active and/or passive device and the at least one passive device. The noise isolator can completely surrounds the stack. The noise isolator is preferably porous silicon.

Integrated acoustic thin film resonator

A power field effect transistor is disclosed that includes polysilicon gate bodies (,) and (,), which includes platinum silicide contact layers (,) and (,) disposed on the outer surfaces of bodies (,) and (,), respectively. In addition, the device comprises an n&plus;drain region (,) which also has a platinum silicide drain contact layer (,) formed on its outer surface and platinum silicide source contact layers (,) and (,). During formation, sidewall spacers (,) and (,), as well as mask bodies (,) and (,) are used to ensure that platinum silicide layer (,) spaced apart from both gate bodies (,) and (,) and platinum silicide gate contact layers (,) and (,).

Power transistor with silicided gate and contacts

A vertical transistor (70) comprising a first semiconductor layer (14) of a first conductive type. A gate structure (32) of a second conductive type disposed on the first semiconductor layer (14). The gate structure (32) may include a plurality of gates (38) separated by channels (40). A second semiconductor layer (50) of the first conductive type may be disposed over the gate structure (32) and in the channels (40). An arresting element (36) may be disposed between and upper surface of the gates (38) and the second semiconductor layer (50). A void (52) may be formed in the second semiconductor layer (50) over the gate (38).

Vertical transistor and method

A multiple peak resonant tunneling diode (10) includes multiple vertical semiconductor structures (12, 13). The vertical structures (12, 13) include a resonant tunneling diode having a predetermined cross-sectional area and a series resistor of a predetermined resistance. The vertical structures (12, 13) are spaced from one another and interconnected in parallel. Additionally, the vertical semiconductor structures (12, 13) are fabricated such that their predetermined diode cross-sectional areas and series resistances have values that vary by predetermined amounts to adjust the respective peak currents and/or peak voltages of the vertical semiconductor structures (12, 13).

Multiple peak resonant tunneling diode

A voltage regulator (10) comprising a vertical channel transistor (12). The vertical channel transistor (12) may have a gate (16), a voltage input terminal (18), and a voltage output terminal (20). A reference voltage supply (14) may be coupled to the gate (16).

Integrated voltage regulator circuit with vertical transistor

A vertical field effect transistor (700) and fabrication method with buried gates (704) having gate sidewall crystal orientation the same as the substrate surface and a low index substrate crystal orientation without tilt to a higher index direction. The gate (704) may have modulated doping along the channel (706), and the drain (708) may have a lighter doping level than the channel which may be accomplished by an epitaxial overgrowth of the gates (704) to form the channels (706).

Vertical JFET field effect transistor

An optical device for sensing properties in an environment such as the presence of a substance or chemical in the zone to be monitored using optical components integrated on a microchip base or substrate. A preferred embodiment introduces a method for fabricating a miniature microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 48 and a silicon photosensor 16 on the same chip. Light 18 is emitted at the edge of the GaAs LED 14. A portion of the light propagates is detected by a PIN diode 16. A chemical sensitive material 50 is coated on top of a polyimide waveguide 48. When the gas or chemical to which the material is sensitive appears, the light transmitted from the polyimide to air increases, thus the total signal sensed by the photodetector decreases, whereby the change in light signal indicates detection.

Integrated microchip chemical sensor

A method and structure is given for flip-chip mounting an integrated circuit on a substrate. An embodiment of the present invention is a GaAs die flip-chip 14 mounted to a silicon semiconductor 10 which has additional processing circuitry. The flip-chip bond uses an alloy metal film, preferably a thin film of AuGe 38, 40. The invention gives a high temperature bond which is suitable for subsequent high temperature processes to be performed on the flip-chip mounted combination. The bond may also include a diffusion barrier 36 which provides a short circuit free LED contact. A preferred embodiment introduces a microchip chemical sensor by integrating a GaAs LED 14 with a polyimide waveguide 56 and a silicon photosensor 16 on the same chip.

Flip-chip die attachment for a high temperature die to substrate bond

Vertical field effect transistor and method

A vertical field effect transistor (1700) and fabrication method with buried gates (1704) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure is disclosed. The vertical field effect transistor elements (1702, 1704, 1706, 1708, 1720, 1724) are made of III-V semiconductor compound grown on a germanium substrate (1726).

Method of making a vertical FET using epitaxial overgrowth

A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact (36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.

Bipolar transistor having a self emitter contact aligned

This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44. Other devices and methods are also disclosed.

Method of making power VFET device

Growing community of inventors

Dallas, TX, United States of America

Han-Tzong Yuan