Silicon Storage Technology, Inc.

Han Tran

Hieu Van Tran

Thuan Vu

Stanley Hong

Hien Pham

Anh Ly

Kha Nguyen

Stephen Trinh

Vipin Tiwari

Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation.

Analog neural memory array in artificial neural network with source line pulldown mechanism

In one example, a neural network device comprises a first plurality of synapses configured to receive a first plurality of inputs and to generate therefrom a first plurality of outputs, wherein the first plurality of synapses comprises a plurality of memory cells, each of the plurality of memory cells configured to store a weight value corresponding to a number of electrons on its floating gate and the plurality of memory cells are configured to generate the first plurality of outputs based upon the first plurality of inputs and the stored weight values.

Neural network device

Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

Read and programming decoding system for analog neural memory

Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

Decoders for analog neural memory in deep learning artificial neural network

Numerous embodiments are disclosed for accessing redundant non-volatile memory cells in place of one or more rows or columns containing one or more faulty non-volatile memory cells during a program, erase, read, or neural read operation in an analog neural memory system used in a deep learning artificial neural network.

Redundant memory access for rows or columns containing faulty memory cells in analog neural memory in deep learning artificial neural network

Various embodiments of word line decoders, control gate decoders, bit line decoders, low voltage row decoders, and high voltage row decoders and various types of physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. Shared and segmented embodiments of high voltage row decoders are disclosed.

Decoding system and physical layout for analog neural memory in deep learning artificial neural network

Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

Growing community of inventors

Ho Chi Minh, Vietnam

Han Tran