Taiwan Semiconductor Manufacturing Comp. Ltd.

Han-Ting Tsai

Chung-Te Lin

Tai-Yen Peng

Wei-Chih Wen

Chien-Min Lee

Hui-Hsien Wei

Pin-Ren Dai

Wei-Yuan Lu

Sheng-Chih Lai

Chun-Fai Cheng

An-Shen Chang

Ming-Huan Tsai

Cheng-Yi Wu

Tsann Lin

Yu-Feng Yin

Qiang Fu

Min-Kun Dai

Haiting Wang

Ka-Hing Fung

Yimin Huang

Kuan-Chung Chen

Wei-Gang Chiu

Jyu-Horng Shieh

Chun-Feng Nieh

Wei-Han Fan

Li-Ping Huang

Hsien-Ching Lo

I-Cheng Chang

Yi-Wei Chiu

Chii-Ming M Wu

Katherine H Chiang

Joung-Wei Liou

Li-Te Hsu

Yen-Chieh Huang

Pin-Cheng Hsu

Ming-Shuan Li

Shih-Ho Lin

Yen-Chung Ho

Chin-Hsing Lin

Bo-Jhih Shen

Jinn-Kwei Liang

Hsueh-Jen Yang

Fung Ka Hing

Kuang-I Liu

Wei-Ching Wang

Yu-Ming Lin

Kai-Hsuan Lee

Hsiang-Ku Shen

Min Cao

Chin-Szu Lee

Kuo-Chang Chiang

Yu-Teng Dai

Cheng-Yu Yang

Szu-Hua Wu

Jung-Tang Wu

Yu-Jen Chien

Ya-Ling Lee

Wu Meng Yu

Sai-Hooi Yeong

Yen-Ming Chen

Tsung-Lin Lee

Dian-Hau Chen

Hsueh-Chang Sung

Chih-Yu Chang

Ken-Ichi Goto

Chien-Hua Huang

Chia-Cheng Ho

Ming-Shiang Lin

Rainer Yen-Chieh Huang

Tzung-Yi Tsai

Gao-Ming Wu

Chang-Lin Yang

Hui-Min Lin

A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.

Transistor including a hydrogen-diffusion barrier and methods for forming the same

A semiconductor device includes a substrate, a gate electrode, a gate dielectric layer, a channel layer, a source electrode and a drain electrode. The gate electrode is disposed over the substrate. The gate dielectric layer is disposed over the gate electrode. The channel layer is disposed over the gate dielectric layer. The source electrode and the drain electrode are disposed over the channel layer and beside the gate electrode. In some embodiments, each of the source electrode and the drain electrode includes a glue layer and a metal pattern, and a thickness of the glue layer adjacent to a sidewall of the metal pattern is greater than a thickness of the glue layer adjacent to a bottom of the metal pattern.

Thin film transistor featuring variable thickness glue layer with tapered end

An integrated circuit device includes a ferroelectric layer that is formed with chlorine-free precursors. A ferroelectric layer formed according to the present teaching may be chlorine-free. Structures adjacent the ferroelectric layer are also formed with chlorine-free precursors. The absence of chlorine in the adjacent structures prevents diffusion of chlorine into the ferroelectric layer and prevents the formation of chlorine complexes at interfaces with the ferroelectric layer. The ferroelectric layer may be used in a memory device such as a ferroelectric field effect transistor (FeFET). The absence of chlorine ameliorates time-dependent dielectric breakdown (TDDB) and Bias Temperature Instability (BTI).

Memory device and method for fabricating the same

In an embodiment, a device includes: a magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, where a first column of the columns includes: first bottom electrodes arranged along the first column; first magnetic tunnel junction (MTJ) stacks over the first bottom electrodes; a first shared electrode over each of the first MTJ stacks; second bottom electrodes arranged along the first column; second MTJ stacks over the second bottom electrodes; a second shared electrode over each of the second MTJ stacks; and a bit line electrically connected to the first shared electrode and the second shared electrode.

Magnetic tunnel junction device and method

Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as HfZrOwith an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.

Method of forming ferroelectric memory device

A memory array device includes an array of memory cells located over a substrate, a memory-level dielectric layer laterally surrounding the array of memory cells, and top-interconnection metal lines laterally extending along a horizontal direction and contacting a respective row of top electrodes within the memory cells. Top electrodes of the memory cells are planarized to provide top surfaces that are coplanar with the top surface of the memory-level dielectric layer. The top-interconnection metal lines do not extend below the horizontal plane including the top surface of the memory-level dielectric layer, and prevent electrical shorts between the top-interconnection metal lines and components of memory cells.

Top-interconnection metal lines for a memory array device and methods for forming the same

A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.

Integrated circuit device

In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.

Magnetic random access memory and manufacturing method thereof

A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

Semiconductor structure and method of forming the same

A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Magnetic tunnel junction device and method of forming same

An IC structure comprises a substrate, a first dielectric structure, a second dielectric structure, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first dielectric structure is over the memory region. The second dielectric structure laterally extends from the first dielectric structure to over the logic region. The second dielectric structure has a thickness less than a thickness of the first dielectric structure. The first via structure extends through the first dielectric structure. A top segment of the first via structure is higher than a top surface of the first dielectric structure. The first memory cell structure is over the first via structure.

Integrated circuit structure

A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Semiconductor device including vertical routing structure and method for manufacturing the same

A method of characterizing a wide-bandgap semiconductor material is provided. A substrate is provided, which includes a layer stack of a conductive material layer, a dielectric material layer, and a wide-bandgap semiconductor material layer. A mercury probe is disposed on a top surface of the wide-bandgap semiconductor material layer. Alternating-current (AC) capacitance of the layer stack is determined as a function of a variable direct-current (DC) bias voltage across the conductive material layer and the wide-bandgap semiconductor material layer. A material property of the wide-bandgap semiconductor material layer is extracted from a profile of the AC capacitance as a function of the DC bias voltage.

Wide-bandgap semiconductor layer characterization

A device includes a resistance switching layer, a capping layer, a top electrode, a first spacer, and a second spacer. The resistance switching layer is over a substrate. The capping layer is over the resistance switching layer. The top electrode is over the capping layer. The first spacer lines the resistance switching layer and the capping layer. The second spacer lines the first spacer. The capping layer is in contact with the top electrode, the first spacer, and the second spacer.

Semiconductor device

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Kaoshiung, Taiwan

Han-Ting Tsai