Macronix International Co., Ltd.

Macronix Internationalco., Ltd.

Han-Sung Chen

Chun-Hsiung Hung

Chung-Kuang Chen

Nai-Ping Kuo

Su-Chueh Lo

Kuo-Yu Liao

Hsin-Yi Ho

Tzeng-Huei Shiau

Tseng-Yi Liu

Ming-Chao Lin

Ken-Hui Chen

Shuo-Nan Hung

Ming-Chih Hsieh

Chuan-Ying Yu

Wen-Pin Tsai

Ching-Chung Lin

Lung-Yi Kuo

Kuen-Long Chang

Ray-Lin Wan

Chun Hsiung Hung

Ho-Chun Liou

Shih-Chang Huang

Ray L Wan

Chih-He Chiang

Chen-Hao Po

Ching-chung Lin

Wen-Yi Hsieh

Yung-Feng Lin

Tom D Yiu

Fuchia Shone

Yu-Shen Lin

Chia-Hsing Chen

Cheng-Jye Liu

I-Long Lee

Shih-Chou Juan

Chung Kuang Chen

Hsien-Hung Wu

Chia-Ching Li

Hsin Yi Ho

Chien-Fu Huang

Chung-Hsiung Hung

Yuan-Chang Liu

Kun-Tse Lee

Tzung-Shen Chen

Jin-Lien Lin

Chia-Yen Yeh

Tso-Ming Chang

Jen-Hung Huang

Chung-Cheng Tsai

Lung Yi Kuo

A memory device and a programming method thereof are provided. The programming method includes the following steps. According to a step value, based on an incremental step pulse programming scheme, multiple programming operations are performed for a selected memory page. In a setting mode, multiple program verify operations are respectively performed corresponding to the programming operations to respectively generate multiple pass bit numbers. In the setting mode, a pass bit number difference value of two pass bit numbers corresponding to two programming operations is calculated. In the setting mode, an amount of the step value is adjusted according to the pass bit number difference value.

Memory device and programming method thereof

A memory having a plurality of blocks is coupled with control circuits having logic to execute a no-current read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks while disabling current flow. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include, respectively, a plurality of sub-blocks. The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.

Fast interval read setup for 3D memory

A memory having a plurality of blocks is coupled with control circuits having logic to execute a read setup operation, the read setup operation comprising simultaneously applying a read setup bias to a plurality of memory cells of a selected block of the plurality of blocks. Logic to traverse the blocks in the plurality of blocks can apply the read setup operation to the plurality of blocks. The blocks in the plurality of blocks can include respectively a plurality of sub-blocks, The read setup operation can traverse sub-blocks in a block to simultaneously apply the read setup bias to more than one individual sub-block of the selected block. A block status table can be used to identify stale blocks for the read setup operation. Also, the blocks can be traversed as a background operation independent of read commands addressing the blocks.

Fast interval read setup for 3D NAND flash

A memory device has a plurality of blocks of memory cells and a plurality of bit lines, each block including a group of word lines, and a set of NAND strings. Each block in the plurality of blocks of memory cells has a plurality of sub-blocks, each sub-block including a distinct subset of the set of NAND strings of the block selected, and a respective sub-block string select line. Control circuits are configured to execute a program operation including applying word line voltages and string select line voltages at a precharge level to precharge the set of NAND strings in the selected block, then lowering the gate voltages on all the sub-block string select lines of the block, and then lowering the word line voltages on the group of word lines. Thereafter, the program of cells in a selected sub-block is executed.

3D memory program disturbance improvement

A memory device comprises a memory cell array, a plurality of sense amplifiers and a memory controller for controlling the plurality of sense amplifiers. The memory cell array includes a plurality of bit lines, where a bit line is coupled to a plurality of memory cells. A sense amplifier is coupled to a bit line and provides a sensing current to access data from one or more memory cells of the plurality of memory cells corresponding to the bit line. The memory controller performs operations comprising: during a pre-charging stage of a memory access cycle, providing, to a particular sense amplifier, a first voltage; and during a sensing stage of the memory access cycle, providing, to the particular sense amplifier, a second voltage, where the second voltage is a non-zero voltage that is lower than the first voltage.

Sensing a memory device

A memory device includes a memory unit including a plurality of memory cells, and a controller including a storage unit that stores a plurality of operation selections each corresponding to a property of at least one selected memory cell among the plurality of memory cells.

Memory device and memory controlling method

One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.

Memory page buffer with simultaneous multiple bit programming capability

The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise.

Clock integrated circuit

A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a cell and executing a program and program verify operation for the cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the program verify level.

Programming scheme for next starting pulse based on a current program pulse for improving programming speed

A page buffer circuit includes a plurality of page buffers including a first page buffer. The first page buffer is configured to load input data of the first page buffer, and input data of at least one neighboring page buffer. The first page buffer is also configured to apply a bias corresponding to the input data of the first page buffer, and the input data of the at least one neighboring page buffer to a bit line.

Page buffer circuit having bias voltage application unit and operating method of same

A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.

Local word line driver

A method for operating a memory includes receiving an input data set, saving a first level error correcting code ECC for the data in the input data set, saving second level ECCs for a plurality of second level groups of the data in the data set, storing the data set in the memory, and testing the data set to determine whether to use the first level ECC or the second level ECCs. The method includes, if the first level ECC is used, storing a flag enabling use of the first level ECC, else if the second level ECCs are used, storing a flag enabling use of the second level ECCs. The method includes storing the second level ECCs in a replacement ECC memory, and storing a pointer indicating locations of the second level ECCs in the replacement ECC memory.

Dynamic data density ECC

A memory cell undergoing programming is determined as belonging to a particular one of a plurality of second threshold voltage ranges that divide a present threshold voltage range of the particular memory cell. Programming pulses are applied to program the particular memory cell to within the target threshold voltage range. At least one of a program voltage and a total duration of the programming pulses applied to the particular memory cell is varied, depending on the particular second threshold voltage range of the memory cell.

Threshold voltage grouping of memory cells in same threshold voltage range

An operating method of a memory device comprises the following steps: a first page buffer receives a first input data to be programed into a first memory cell of the memory cells; a second page buffer receives a second input data to be programed into a second memory cell of the memory cells; and the first page buffer determines whether to shift a program verify (PV) voltage for the first input data according to the first and second input data.

Memory device and operating method thereof for reducing interference between memory cells

A method for maintaining a data set includes storing a base copy of the data set in a first non-volatile memory having a first writing speed, storing changes to the data set in a first change data set in a second non-volatile memory having a second writing speed, and generating a current copy of the data set by reading the base copy and the changes. If a threshold number of entries in the first change data set is reached, then part or all of the first change data set is moved into a second change data set in the first non-volatile memory, where the generating step includes reading the second change data set. If a threshold number of entries in the second change data set is reached, then the current copy is generated by reading the base copy and the changes in the first and the second non-volatile memory.

Difference L2P method

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Hsinchu, Taiwan

Han-Sung Chen