Samsung Electronics Co., Ltd.

Han-su Pae

Dong-hoon Baek

Jae-youl Lee

Young-min Choi

Jung-Pil Lim

According to an example embodiment, a display driving integrated circuit (IC) includes a timing controller and a plurality of source drivers. The timing controller is configured to output a plurality of signals to the plurality of source drivers, and at least one of the timing controller and the plurality of source drivers operates in a power down mode in at least one of an initializing period, a data transmission period, and a vertical blank period. According to an example embodiment, a mode conversion method used in a display driving IC includes switching between a normal mode to a power down mode in response to a standby control signal. The power down mode is implemented on at least one of a timing controller and a plurality of source drivers included in the display driving IC in at least one of an initializing period, a data transmission period, and a vertical blank period.

Mode conversion method, and display driving integrated circuit and image processing system using the method

A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.

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Hwaseong-si, South Korea

Han-su Pae