Skhynix Inc.

Hynix Semiconductor Inc.

Han-Soo Joo

Sang-Hyun Oh

Seiichi Aritome

Sang-Moo Choi

Eun-Seok Choi

Hyun-Seung Yoo

Byung-Soo Park

Sung-Kye Park

Gyu-Seog Cho

Seok-Kiu Lee

Dong-Kee Lee

Yu-Jin Park

Sung-Joo Hong

A three-dimensional non-volatile memory device that may increase erase operation efficiency during an erase operation using Gate-Induced Drain Leakage (GIDL) current and a method for fabricating the three-dimensional non-volatile memory device. The non-volatile memory device includes a channel structure formed over a substrate including a plurality of inter-layer dielectric layers and a plurality of channel layers that are alternately stacked, and a first selection gate and a second selection gate that are disposed on a first side and a second side of the channel structure, wherein the first selection gate and the second selection gate are disposed on sidewalls of the multiple channel layers, respectively, wherein a work function of a material forming the first selection gate is different from a work function of a material forming the second selection gate.

Non-volatile memory device and method for fabricating the same

A non-volatile memory device having a string of a plurality of memory cells that are serially coupled, wherein the string of memory cells includes a plurality of second channels of a pillar type, a first channel coupling lower end portions of the plurality of the second channels with each other, and a plurality of control gate electrodes surrounding the plurality of the second channels.

3D non-volatile memory device and method for fabricating the same

A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.

Reading method of non-volatile memory device

A method for fabricating a non-volatile memory device includes forming a channel link layer and an isolation layer surrounding the channel link layer over a substrate, forming a stack structure having interlayer dielectric layers that are alternately stacked with gate electrode layers over the channel link layer and the isolation layer, and forming a pair of channels connected to the channel link layer through the stack structure, and a memory layer interposed between the channel and the stack structure.

A nonvolatile memory device includes a gate structure in which a plurality of interlayer dielectric layers and a plurality of gate electrodes are alternately stacked; a pass gate electrode lying under the gate structure; a sub channel hole defined in the pass gate electrode; a pair of main channel holes defined through the gate structure and communicating with the sub channel hole; a channel layer formed on inner walls of the pair of main channel holes and the sub channel hole; and a metallic substance layer contacting the channel layer in the sub channel hole.

Nonvolatile memory device and method for fabricating the same

A method for fabricating a 3D-nonvolatile memory device includes forming a sub-channel over a substrate, forming a stacked layer over the substrate, the stacked layer including a plurality of interlayer dielectric layers that are alternatively stacked with conductive layers, selectively etching the stacked layer to form a first open region exposing the sub-channel, forming a main-channel conductive layer to gap-fill the first open region, selectively etching the stacked layer and the main-channel conductive layer to form a second open region defining a plurality of main channels, and forming an isolation layer to gap-fill the second open region.

Growing community of inventors

Gyeonggi-do, South Korea

Han-Soo Joo