Samsung Electronics Co., Ltd.

Han Seong Kim

Kyu-Hee Han

Jong Min Baek

Woo Kyung You

Sang Shin Jang

Jang Ho Lee

Sung Jin Kang

Young Soo Jeon

Ho Sik Kim

Gi Ho Seo

Kyung Hawn Cho

Chan Sik Park

Won Soon Lee

A semiconductor device including a first interlayer insulating film; a conductive pattern in the first interlayer insulating film; a resistance pattern on the conductive pattern; an upper etching stopper film spaced apart from the resistance pattern, extending in parallel with a top surface of the resistance pattern, and including a first metal; a lower etching stopper film on the conductive pattern, extending in parallel with a top surface of the first interlayer insulating film, and including a second metal; and a second interlayer insulating film on the upper etching stopper film and the lower etching stopper film, wherein a distance from a top surface of the second interlayer insulating film to a top surface of the upper etching stopper film is smaller than a distance from the top surface of the second interlayer insulating film to a top surface of the lower etching stopper film.

Semiconductor device

A semiconductor device having a metal layer pattern which prevents cracks from forming in insulating spaces. The semiconductor device includes a plurality of metal layers stacked vertically and a plurality of insulating layers, interposed vertically between the plurality of metal layers. A metal wiring pattern is formed on each of the plurality of metal layers. The wiring patterns are separated by insulating spaces, and the insulating spaces in each of the plurality of metal layers are vertically shifted with regard to the neighboring one of the plurality of metal layers.

Method of preventing cracks in insulating spaces between metal wiring

A method for forming trench isolation in the silicon substrate is disclosed. This method allows for an improved bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After a trench is formed, sidewall silicon dioxide is grown on the sidewall of the trench by a first oxidation process. Then, PE-TEOS is deposited on the silicon substrate and the sidewall of the trench. The PE-TEOS layer around the entrance of the trench is then etched back using argon gas. The second oxidation process or the first annealing proceeds to enhance the bonding force between the sidewall silicon dioxide layer and the sidewall of the trench. After the second oxidation process or the annealing, the trench is filled with O.sub.3 -TEOS, and then PE-TEOS is deposited over the O.sub.3 -TEOS layer. Finally, the second annealing process follows.

Method for forming a trench isolation structure comprising an interface

Semiconductor device for avoiding cracks in insulating spaces between

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Suwon, South Korea

Han Seong Kim