Taiwan Semiconductor Manufacturing Comp. Ltd.

Siliconware Precision Industries Co., Ltd.

Han-Ping Pu

Kai-Chiang Wu

Yu-Feng Chen

Chien-Ping Huang

Chao-Wen Shih

Cheng-Hsu Hsiao

Chen-Hua Douglas Yu

Hsin-Yu Pan

Ting-Chu Ko

Albert Wan

Chun-Hung Lin

Chun-Lin Lu

Sen-Kuei Hsu

Ming-Kai Liu

Chung-Shi Liu

Yung-Ping Chiang

Yu-Sheng Hsieh

Chang-Wen Huang

Chuei-Tang Wang

Ching-Hua Hsieh

Chang-Fu Lin

Chien Ping Huang

Ching-Yu Huang

Ming-Da Cheng

Hung-Jui Kuo

Chung-Hao Tsai

Tsung-Shu Lin

Chih-Ming Huang

Yu-Chen Hsu

Hao-Yi Tsai

Chen-Shien Chen

Tin-Hao Kuo

Ming-Che Ho

Meng-Tse Chen

Yen-Ping Wang

Hsiao-Wen Lee

Chien-Ling Hwang

Chi-Chuan Wu

Nan-Chin Chuang

Yu-Ling Tsai

Yuh Chern Shieh

Pei-Haw Tsao

Hui-Jung Tsai

Shih-Kuang Chiu

Pei-Hsuan Lee

Yu-Po Wang

Tzu-Chun Tang

Randy H Y Lo

Sheng-Hsiang Chiu

Lipu Kris Chuang

Yu-Ting Chiu

Jui-Chang Kuo

Der-Chyang Yeh

Mirng-Ji Lii

Tsung-Ding Wang

Chien Ling Hwang

Yi-Wen Wu

Chih-Hang Tung

Shou-Zen Chang

Tsung-Fu Tsai

Jung Wei Cheng

Kim Hong Chen

Yian-Liang Kuo

Kuo-Chin Chang

Guan-Yu Chen

Ho-Yi Tsai

Ying-Chou Tsai

Chi-Ming Huang

Hsien-Liang Meng

Ming-Song Sheu

Fang-Lin Tsai

Yih-Jenn Jiang

Chung-Yi Hsu

Hsien-Wei Chen

Wen-Chih Chiou

Shang-Yun Hou

Jiun Yi Wu

Fu-Lung Hsueh

Ching-Wen Hsiao

Chen-Cheng Kuo

Mill-Jer Wang

Yu-Chih Huang

Chun-Cheng Lin

Chih-Chin Liao

Kai-Ming Ching

Ming Hsien Tsai

Chieh-Yen Chen

Kuo-Lung Pan

Yu-Jen Cheng

Chang-Chia Huang

Hao-Juin Liu

Min-Chien Hsiao

Sa-Lly Liu

Bai-Yao Lou

Tzong-Dar Her

Eric Ko

Wei-Sen Chang

Chin-Te Chen

Dean Wang

Yu Yi Huang

A method includes forming a dielectric layer over a contact pad of a device, forming a first polymer layer over the dielectric layer, forming a first conductive line and a first portion of a second conductive line over the first polymer layer, patterning a photoresist to form an opening over the first portion of the second conductive feature, wherein after patterning the photoresist the first conductive line remains covered by photoresist, forming a second portion of the second conductive line in the opening, wherein the second portion of the second conductive line physically contacts the first portion of the second conductive line, and forming a second polymer layer extending completely over the first conductive line and the second portion of the second conductive line.

Conductive traces in semiconductor devices and methods of forming same

A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Stacked memory cube with integrated thermal path for enhanced heat dissipation

Semiconductor packages and methods of forming the same are disclosed. An semiconductor package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Semiconductor packages and methods of forming the same

In accordance with some embodiments a via is formed over a semiconductor device, wherein the semiconductor device is encapsulated within an encapsulant. A metallization layer and a second via are formed over and in electrical connection with the first via, and the metallization layer and the second via are formed using the same seed layer. Embodiments include fully landed vias, partially landed vias in contact with the seed layer, and partially landed vias not in contact with the seed layer.

Semiconductor device and method

A memory device including a first semiconductor die and a memory cube mounted on and connected with the first semiconductor die is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes second semiconductor dies laterally wrapped by an encapsulant and a redistribution structure disposed on the second semiconductor dies and the encapsulant. The second semiconductor dies of the multiple stacked tiers are electrically connected with the first semiconductor die through the redistribution structures in the multiple stacked tiers. Each redistribution structure in the multiple stacked tiers includes redistribution patterns, the redistribution structure closest to the first semiconductor die further includes a thermally conductive layer connected to the first semiconductor die, wherein a material of the redistribution patterns in the multiple stacked tiers is different from a material of the thermally conductive layer of the redistribution structure closest to the first semiconductor die, and the thermally conductive layer is electrically isolated from the second semiconductor dies in the multiple stacked tiers and the first semiconductor die.

Memory device and manufacturing method thereof

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.

Semiconductor package and manufacturing method thereof

A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.

Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof

The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

Integrated fan-out packaging

A semiconductor device including a chip package, a dielectric structure, and a first antenna pattern is provided. The dielectric structure is disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern is disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern.

Semiconductor device having antenna and manufacturing method thereof

Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes two dies, an encapsulant, a first metal line and a plurality of dummy vias. The encapsulant is disposed between the two dies. The first metal line is disposed over the two dies and the encapsulant, and electrically connected to the two dies. The plurality of dummy vias is disposed over the encapsulant and aside the first metal line.

Integrated fan-out packages and methods of forming the same

Semiconductor device having antenna on chip package and manufacturing method thereof

Growing community of inventors

Taichung, Taiwan

Han-Ping Pu