Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Han-Min Tsai

Chi-Feng Huang

Victor Chiang Liang

Chia-Chung Chen

Fu-Huan Tsai

Tzu-Jin Yeh

Hsieh-Hung Hsieh

Hong-Lin Chu

Hsiao-Chun Lee

Shu-Fang Fu

Shou-Chun Chou

Sheng-Hung Wang

Hung-Chih Luan

He-Yuan Yang

Ting-Yi Kuo

Pi-Fei Tsai

A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

High-implant channel semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is implanted in the first region of the fins but not in the second regions. A gate structure overlies the first region of the fins and source/drains are formed on the second regions of the fins.

Buried channel semiconductor device and method for manufacturing the same

FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.

FinFET varactor with low threshold voltage and method of making the same

The present invention provides a display device, including: a first chromatic light source configured to generate first chromatic light, a dichroic reflection layer disposed on a light emergent side of the first chromatic light source and allowing the first chromatic light to pass through, and a quantum dot layer. The dichroic reflection layer has a first surface facing away from the first chromatic light source, and the first surface has a plurality of recessed portions. The quantum dot layer includes a plurality of quantum dot blocks, and the quantum dot blocks are disposed corresponding to the recessed portions.

Display device comprising a dichroic reflection layer having a plurality of recessed portions disposed with a corresponding plurality of quantum dot blocks

Disclosed is a FinFET varactor with low threshold voltage and methods of making the same. A disclosed method includes receiving a semiconductor layer over a substrate and having channel, source, and drain regions. The method includes forming a well in the semiconductor layer to have a first dopant, and implanting a second dopant into the well. The first and second dopants are of opposite doping types. A first portion of the well has a higher concentration of the second dopant than the first dopant. A second portion of the well under the first portion has a higher concentration of the first dopant than the second dopant. The method further includes forming a gate stack over the channel region, and forming source and drain features in the source and drain regions. The first portion of the well electrically connects the source and drain features.

A bipolar junction transistor includes an emitter, a base contact, a collector and a shallow trench isolation. The base contact has two base fingers that form a corner to receive the emitter. The collector has two collector fingers extending along the base fingers of the base contact. The shallow trench isolation is disposed in between the emitter and the base contact and in between the base contact and the collector.

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Hsinchu, Taiwan

Han-Min Tsai