Samsung Electronics Co., Ltd.

Han-Mei Choi

Young-sun Kim

Ki-Hyun Hwang

Sung-Tae Kim

Seung-Hwan Lee

Ki-chul Kim

Dong-Chul Yoo

Bong-jin Kuh

Seung-hwan Lee

Ki-yeon Park

Kyoung-Ryul Yoon

Young-Geun Park

Dae-Sik Choi

Tae-Gon Kim

In-Sung Park

Ki-Yeon Park

Young-Sun Kim

Se-hoon Oh

Eun-ha Lee

Jun-Kyu Yang

Jong-Hoon Kang

Sun-jung Kim

Byong-Ju Kim

Cha-young Yoo

Jae-Soon Lim

Yun-Jung Lee

Young-Wook Park

Gab-Jin Nam

Kyoung-Seok Kim

Jong-sung Lim

Joong-han Shin

Eun-Taek Yim

Eun-Young Jo

Kyung-Hyun Kim

Young-wook Park

Jae-young Ahn

Byung-Hong Chung

Sung Heo

Chan-Jin Park

Phil-Ouk Nam

Sun-Jung Kim

Kyong-Won An

Hyung-Ik Lee

In-Sun Yi

Dong-chul Yoo

Min-kyung Ryu

Wanit Manorotkul

Dmitry Mikulik

Chang-Hyun Lee

Yong-Hoon Son

Ji-Eun Lee

Si-Young Choi

Jin-Gyun Kim

Jung-Min Oh

Jong-Cheol Lee

Myoung-Bum Lee

Wan-don Kim

Cha-Young Yoo

Byoung-Moon Yoon

Young-sub You

Kwang-Hee Lee

Jung-hee Chung

Hong-suk Kim

Hyo-Jung Kim

Je-Woo Han

Seung-Jae Baik

Gyung-Jin Min

Joon-Suk Lee

Jong-Heun Lim

Yeon-Sil Sohn

Chang-Sup Mun

Nam-goo Cha

Jeong-hee Chung

Bi-O Kim

Sang-Ryol Yang

Zong-liang Huo

Kwang-Min Park

Jun-ho Yoon

Won-Bong Jung

Jin-I Lee

Jung-Yun Won

Cha-Dong Yeo

Kwang-Chul Park

Young-Hee Kim

Sang-ryol Yang

Yong-Koo Kyoung

Sang-Yoon Woo

Soo-Doo Chae

Dong-Jo Kang

Myeong-Jin Kim

Tae-Jin Park

Yong-Moon Jang

Myung-Jung Pyo

Ju-Yul Lee

Jae-Hyoung Choi

Beung-Keun Lee

Gab-jin Nam

Jong-wan Kwon

Jeong-meung Kim

Soon-wook Jung

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.

Vertical memory devices and methods of manufacturing the same

There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type semiconductor, a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer, a plurality of nanocores disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor, an active layer disposed on surfaces of the plurality of nanocores positioned to be higher than the first insulating layer, a second insulating layer disposed on the first insulating layer and having a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores, and a second conductivity-type semiconductor layer disposed on the surface of the active layer positioned to be higher than the second insulating layer.

Nano-structured semiconductor light-emitting element

An IC device includes a polycrystalline silicon thin film interposed between a first level semiconductor circuit and a second level semiconductor circuit which are formed on a substrate and disposed to vertically overlap each other. The polycrystalline silicon thin film includes at least one silicon single crystal. The at least one silicon single crystal includes a flat horizontal portion, which provides an active region of the second level semiconductor device, and a pin-shaped protruding portion protruding from the flat horizontal portion toward the first level semiconductor device.

Integrated circuit device including polycrystalline semiconductor film and method of manufacturing the same

According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

Method of fabricating semiconductor device having preliminary stacked structure with offset oxide etched using gas cluster ion

A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.

Method of manufacturing semiconductor device having doped layer

A semiconductor device includes a single crystalline substrate, an electrical element and an optical element. The electrical element is disposed on the single crystalline substrate. The electrical element includes a gate electrode extending in a crystal orientation &#x3c;110&#x3e; and source and drain regions adjacent to the gate electrode. The source region and the drain region are arranged in a direction substantially perpendicular to a direction in which the gate electrode extends. The optical element is disposed on the single crystalline substrate. The optical element includes an optical waveguide extending in a crystal orientation &#x3c;010&#x3e;.

Semiconductor devices

A vertical memory device includes a channel, a ground selection line (GSL), word lines, a string selection line (SSL), and a contact. The channel includes a vertical portion and a horizontal portion. The vertical portion extends in a first direction substantially perpendicular to a top surface of a substrate, and the horizontal portion is connected to the vertical portion and parallel to the top surface of the substrate. The GSL, the word lines and the SSL are formed on a sidewall of the vertical portion of the channel sequentially in the first direction, and are spaced apart from each other. The contact is on the substrate and electrically connected to the horizontal portion of the channel.

A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.

Methods of forming epitaxial layers

A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.

Integrated circuit devices including electrode support structures and methods of fabricating the same

An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening.

Methods of manufacturing a semiconductor device

Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Methods of manufacturing semiconductor devices

Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.

Method of fabricating semiconductor device

A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.

Method for fabricating nonvolatile memory device

A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.

Method of fabricating nonvolatile memory device

Growing community of inventors

Seoul, South Korea

Han-Mei Choi