Silicon Integrated Systems Corporation

Phoenix Precision Technology Corporation

Han-Kun Hsieh

Wei-Feng Lin

I-Chung Tung

Shih-Ping Hsu

Yi-Chang Hsieh

Shing-Ru Wang

A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.

Formation of electroplate solder on an organic circuit board for flip chip joints and board to board solder joints

A padless high density circuit board and manufacturing method thereof. The method includes providing a circuit board substrate, forming external wiring, having a plurality of external terminals with a width as large as or less than the external wiring on the circuit board substrate, forming a solder mask over the circuit board substrate and the external wiring with a plurality of solder mask openings exposing the external terminals, with diameters at least as large as the widths of the external terminals exposed thereby, and forming a plurality of conductive bumps on the external terminals exposed by the solder mask openings for connection with an external device in a subsequent assembly process.

Padless high density circuit board

A process for fabricating a flip-chip substrate with metal bumps thereon. A flip-chip substrate is provided with conductive points thereon and a conductive film is formed over the surface of the flip-chip substrate to cover the conductive points. A photoresist layer is formed over the conductive layer and then patterned to form openings exposing the underlying conductive points. A copper plating is performed to fill the openings as copper bumps. The photoresist layer and the conductive film are removed. Finally, a solder mask layer is formed over the flip-chip substrate and exposing the copper bumps and an anti-oxidation treatment is performed to finish exposing the copper bumps.

Method for fabricating conductive bumps and substrate with metal bumps for flip chip packaging

A flip chip assembly process forming an underfill encapsulant. The method includes providing a chip having an active surface and a plurality of conductive bumps arranged in array with a predetermined bump pitch thereon, providing a substrate having a surface, having a die-attaching region, having a plurality of pads with previously formed solder paste thereon, arranged in array with a predetermined pad pitch the same as the active surface, forming an encapsulant in the die-attaching region excluding the pads, using a stencil and screen printing, and attaching the chip onto the substrate resulted from one-to-one joining the conductive bumps and the pads. A tool forming an underfill encapsulant is includes a stencil having at least one printing region, including a plurality of openings, a plurality of covers arranged in array with a predetermined cover pitch, and a plurality of connecting devices, connecting every two neighboring covers, or each cover with other regions of the stencil.

Flip chip assembly process for forming an underfill encapsulant

A chip-packaging substrate and test method therefor. The chip-packaging substrate includes at least one package area and a connection area enclosed by and connected to the package areas. A test circuit is arranged within the connection area, passing through at least two wire layers and the insulation layer therebetween. The test circuit electrically connects the first electrodes. Failure of the chip-packaging substrate is detected when the test circuit is open between any two electrodes.

Chip-packaging substrate and test method therefor

Disclosed is a method of preparing a thin core substrate for fabricating a build-up multilayer circuit board. The method involves the use of an insulating layer which is covered with the electrically conductive sheets. The openings are made in the electrically conductive layers at the predetermined positions, where the vias are also formed in the insulating layer. An electrically conductive layer is deposited to cover the vias. After the electrically conductive sheets and layer are patterned, a thin core substrate is constructed. The build-up layers are then made at least one side of the thin core substrate to form a build-up multilayer circuit board.

Growing community of inventors

Miaoli, Taiwan

Han-Kun Hsieh