Samsung Electronics Co., Ltd.

Han-Ku Cho

Gi-Sung Yeo

Sang-Gyun Woo

Suk-Joo Lee

Ji-young Lee

Doo-youl Lee

Sang-jun Choi

Joon-Soo Park

Doo-Hoon Goo

Cha-Won Koh

Jung-hyeon Lee

Sung-Gon Jung

Jeong-lim Nam

Kyoung-Yun Baek

Suk-joo Lee

Hyun-woo Kim

Chan Soo Hwang

Pan-suk Kwak

Chil-Hee Chung

Hai-sub Na

Sung-Soo Suh

Joo-Tae Moon

Cha-won Koh

Tae-young Kim

Seong-sue Kim

Woo-Gwan Shim

Yool Kang

Sung-Woo Lee

Byeong-Soo Kim

Chang-jin Kang

Si-hyeung Lee

Jung-hwan Hah

Kyoung-seon Kim

Jin-hong Park

Chang-Ki Hong

Sung-min Chi

Sung-Chan Park

Hyun-Jae Kang

Mitsuhiro Hata

Young-Mi Lee

Chang-Sup Mun

Won-Sun Kim

Young-Chang Kim

Man-hyoung Ryoo

Chang-Min Park

Young-Seog Kang

Yong-Jin Chun

Doo-Won Kwon

Joon-soo Park

Jang-Ho Shin

Min-jong Hong

Duo-Hoon Goo

Joo-Tac Moon

Jae-ok Yoo

Provided are a coating composition for deep ultraviolet (DUV) filtering during an extreme ultraviolet (EUV) exposure, the coating composition including about 100 parts by weight of a solvent including a first solvent (the first solvent being an alcoholic solvent); and about 0.05 parts by weight to about 5 parts by weight of a coating polymer having a degree of absorption of about 50%/&#x3bc;m or greater with respect to 193-nm incident light.

Coating composition for DUV filtering, method of forming photoresist pattern using the same and method of fabricating semiconductor device by using the method

An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.

Oligomer probe array and method of producing the same

A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask.

Method of forming a hard mask and method of forming a fine pattern of semiconductor device using the same

A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.

Method of forming fine patterns of semiconductor device

A semiconductor memory device may include a semiconductor substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a drain portion of a respective active region of each column, and with each bitline crossing drain portions of active regions of adjacent columns in different directions so that different portions of a same bitline are aligned in different directions on different active regions of adjacent columns.

Semiconductor memory devices including diagonal bit lines

A semiconductor memory device may include a substrate having a plurality of active regions wherein each active region has a length in a direction of a first axis and a width in a direction of a second axis. The length may be greater than the width, and the plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis. A plurality of wordline pairs may be provided on the substrate, with each wordline pair crossing active regions of a respective column of active regions defining a drain portion of each active region between wordlines of the respective wordline pair. A plurality of bitlines on the substrate may cross the plurality of wordline pairs, with each bitline being electrically coupled to a respective drain portion of an active region of each column, and with each bitline being arranged between the respective drain portion and another drain portion of an adjacent active region of the same column.

Semiconductor memory devices including offset bit lines

Provided are a compensating mask, a multi-optical system using the compensating mask, and a method of compensating for a 3-dimensional (3-D) mask effect using the compensating mask. Methods of compensating for a 3-D mask effect using a compensating mask may include generating a first kernel corresponding to a normal mask used for forming a minute pattern, generating a second kernel corresponding to a compensating mask, mixing the first kernel corresponding to the normal mask with the second kernel corresponding to the compensating mask, and generating a multi-optical system kernel corresponding to mixing the first kernel and the second kernel.

Compensating masks, multi-optical systems using the masks, and methods of compensating for 3-D mask effect using the same

An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models. A first example method may include storing a first plurality OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics, generating an IC layout, selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the first plurality of OPC models and the generated IC layout and generating a mask layout based on the generated IC layout and the selected second plurality of OPC models. A second example method may include applying a first OPC model to a first portion of a generated integrated circuit (IC) layout, applying a second OPC model to a second portion of the generated IC layout and generating a mask layout based on the generated IC layout after the application of the first and second OPC models.

System and method correcting optical proximity effect using pattern configuration dependent OPC models

A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based Self-Aligning Double Patterning (SADP) emulation, comparing the first emulation pattern with the first mask data pattern, and modifying the second mask data pattern according to results of the comparison. The method further includes performing Optical Proximity Correction (OPC) on the modified second mask data pattern, acquiring second emulation patterns, which are predicted from the second mask data pattern on which the OPC has been performed, using image-based SADP emulation, and comparing the second emulation patterns and the first mask data pattern and manufacturing a first mask layer, which corresponds to the second mask data pattern on which the OPC has been performed, according to the results of the comparison.

Method of manufacturing a mask

A method of forming a semiconductor device includes forming a first mask pattern on a target layer, the first mask pattern exposing a first portion of the target layer, forming an intermediate material layer, including depositing an intermediate material layer film on a side of the first mask pattern and the first portion of the target layer, and thinning the intermediate material layer film to form the intermediate material layer, forming a second mask pattern that exposes a second portion of the intermediate material layer, removing the exposed second portion of the intermediate material layer to expose the target layer, and patterning the target layer using the first and second mask patterns as patterning masks.

Method of forming a semiconductor device

A reflective photomask for EUV light is disclosed. The reflective photomask may include a projecting pattern selectively formed on a substrate and a reflective layer on the substrate and the projecting pattern.

Reflective photomask and method of fabricating the same

An optical mask for use with an exposure beam includes a mask substrate adapted to be placed on a traveling path of the exposure beam. A reference pattern is formed on the mask substrate. The reference pattern is adapted to direct the exposure beam to travel in a predetermined reference direction. A comparative pattern is formed on the mask substrate. The comparative pattern is adapted to direct the exposure beam to travel in a direction inclined at a predetermined angle with respect to the reference direction.

Optical masks and methods for measuring aberration of a beam

A semiconductor device having a fin type active area includes a plurality of active regions, a first device isolation layer and a recessed second device isolation layer disposed in a direction of gate electrodes of the semiconductor device. A recessed second device isolation layer and a first device isolation layer are disposed in a vertical direction of the gate electrodes. The first device isolation layer and the plurality of active regions are alternately disposed in a first direction of the plurality of active regions.

Semiconductor devices having Fin-type active areas and methods of manufacturing the same

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Seongnam-si, South Korea

Han-Ku Cho