Ag Communication Systems Corporation

Han Kem

John S Young

Robert E Renner

Kuang-Cheng Hu

A data adapter for simultaneously providing a low speed channel, a first high speed data channel, and a second high speed channel over a two wire connection; the two wire connection connects the data adapter to a telephone system. The data adapter includes a line transceiver connected to the two-wire connection, the line interface provides a full duplex transmission link with the telephone system over the two-wire connection. A telephone interface converts data between the first high speed channel and a telephone instrument. A rate adapter converts data between the second high speed channel and a data processing equipment. A protocol controller performs a packet protocol on the low speed channel, and routes the first high speed channel to the telephone interface and the second high speed channel to the rate adapter. A processor that receives and transmits messages through the protocol controller over the low speed channel to the telephone system, and in response to information received over the low speed channel, alternatively information received from the rate adapter, the processor controls the data adapter.

Simultaneous voice and data system using the existing two-wire inter-face

A single circuit for detecting a synchronization pattern in a serial data stream. Subsequent to detecting the synchronization pattern, the single circuit generates the control signals for converting the serial data to a parallel format and loading the parallel data into a first-in-first-out (FIFO) memory. The single circuit includes a controller arranged to receive the serial data stream. A counter is connected to the controller. When the counter is detecting the synchronization pattern and the synchronization pattern is being received, the counter is incremented. Absent the synchronization pattern being received, the counter is reset to a predetermined starting point. Subsequent to detecting the synchronization pattern, the counter generates a load signal. The single circuit further includes a pulse generator arranged to receive the load signal from the counter and generate a pulse of duration equal to a bit period of the serial data stream. An indicator is provided which generates an in-synch signal after the counter detects the synchronization pattern.

Single circuit for detecting a frame synchronization pattern and

The circuit of the present invention provides a signal which allows data to be transferred between a first synchronous system to a second synchronous system. Where the first synchronous system is a Time-Division-Multiplexing (TDM) system and the second synchronous system is a Microprocessor system. The transfer is allowed at the end of the assigned time slot provided that the microprocessor is not accessing the data. If the microprocessor is accessing the data, then the transfer is delayed for three clock cycles of the TDM clock. After the delay, if the microprocessor is still accessing the data, the transfer is delayed again. The delaying continues until the microprocessor is no longer accessing the data, at which time the transfer is allowed.

Interface circuit for data transmission between a microprocessor system

An interface circuit which connects a Digital-Signal-Processor (DSP) to a serial controller. The interface circuit includes a bi-directional multiplexer which converts the separate address and data busses of the DSP to the multiplexed data and address bus of the serial controller. A timing generator is included for keeping track of the number of clock cycles in the present access. A decoder connected to the timing generator decodes the number of clock cycles and generates the appropriate control signals to both the serial controller and the DSP.

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Glendale, AZ, United States of America

Han Kem