Skhynix Inc.

Hynix Semiconductor Inc.

Han Jun Bae

Jong Hoon Kim

Jin Ho Bae

Ki Jun Sung

Ju Il Eom

Seung Yeop Lee

Chan Woo Jeong

Woong Hee Lee

Tae Min Kang

Jae Myun Kim

Won Duck Jung

Dae Woong Lee

Jin Kyoung Park

Joo Hyun Kang

A semiconductor package includes a substrate and a sub semiconductor package disposed over the substrate. The sub semiconductor package includes a sub semiconductor chip which has chip pads on its active surface facing the substrate, a sub molding layer which surrounds side surfaces of the sub semiconductor chip and has one surface facing the substrate, and redistribution conductive layers which are connected to the chip pads and extend over the one surface of the sub molding layer. The redistribution conductive layers include a signal redistribution conductive layer, which extends onto an edge of the sub molding layer and has a signal redistribution pad on its end portion, and a power redistribution conductive layer, which has a length shorter than a length of the signal redistribution conductive layer and has a power redistribution pad on its end portion.

Semiconductor package including stacked semiconductor chips

A semiconductor package includes: a sub semiconductor package disposed over a substrate, the sub semiconductor package including a sub semiconductor chip which has chip pads on its upper surface, a molding layer which surrounds side surfaces of the sub semiconductor chip, and a redistribution layer formed over the sub semiconductor chip and the molding layer, the redistribution layer including redistribution conductive layers which are connected to the chip pads of the sub semiconductor chip and extend onto edges of the molding layer while having redistribution pads on their end portions; first sub package interconnectors connected to the redistribution pads to electrically connect the sub semiconductor chip and the substrate; a capacitor formed in the molding layer and including a first electrode, a second electrode, and a body portion, the first and second electrodes having upper surfaces which are connected to the redistribution conductive layers, respectively.

Semiconductor package including capacitor

A semiconductor package includes a molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. The molding member includes an extendible material which includes a first part having a warped shape, a second part extending from one end of the first part to be flat, and a third part extending from the other end of the first part to be flat, where first surfaces of the connectors are exposed at a surface of the molding member and second surfaces of the connectors are coupled to the chip.

Stretchable semiconductor packages and semiconductor devices including the same

A flexible device includes a first conductive pattern, a second conductive pattern, and a dielectric layer. The first conductive pattern includes a first sliding contact portion and a first extension portion. The second conductive pattern includes a second sliding contact portion overlapping with the first sliding contact portion and the second conductive pattern includes a second extension portion. The second sliding contact portion is in contact with the first sliding contact portion and is movable on the first sliding contact portion for a sliding motion. The first and second conductive patterns are embedded in the dielectric layer.

Flexible device including sliding interconnection structure

There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.

Semiconductor packages including heat spreaders and methods of manufacturing the same

A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.

Semiconductor packages including through mold ball connectors on elevated pads and methods of manufacturing the same

A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the molding member. First surfaces of the connectors are exposed at a surface of the molding member, and second surfaces of the connectors are coupled to the chip.

A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. The semiconductor chip includes a tension supplement pattern attached to the second surface and spaced apart from the package substrate.

Semiconductor packages, methods of manufacturing the same, electronic systems including the same, and memory cards including the same

A semiconductor device includes a substrate, an elastic buffer layer disposed on a surface of the substrate, wiring patterns disposed on a first surface of the elastic buffer layer, and a semiconductor chip disposed on a second surface of the elastic buffer layer facing away from the first surface of the elastic buffer layer. The semiconductor chip includes trenches formed on a surface facing the elastic buffer layer. Interconnection members are disposed to electrically connect the elastic buffer layer to the substrate. Each of the interconnection members has one end electrically connected to one of the wiring patterns and the other end electrically connected to the substrate.

Semiconductor package

Stack packages are provided. The stack package includes a first chip configured to include a first chip body having a top surface and a bottom surface, first through electrodes penetrating the first chip body, and an insulation layer disposed on the bottom surface of the first chip body, and first bumps disposed on the top surface of the first chip body, and a second chip configured to include a second chip body having a top surface and a bottom surface, and second bumps disposed on the top surface of the second chip body. The first and second chips are vertically stacked such that the top surface of the second chip body is directly attached to the first insulation layer and the second bumps of the second chip penetrate the first insulation layer of the first chip to pierce the first through electrodes of the first chip.

Stack packages and methods of fabricating the same

A stack package includes a substrate having connection terminals and a first chip on the substrate. The first chip has first connectors on edges thereof. A second chip is stacked on the first chip to expose outer portions of the first connectors. The second chip has second connectors on edges thereof. Connection members to connect the exposed outer portions of the first connectors to the connection terminals. Sidewall interconnectors to connect the exposed outer portions of the first connectors to the second connectors. The sidewall interconnectors extend from the exposed outer portions of the first connectors along sidewalls of the second chip to cover the second connectors.

Stack packages and methods of manufacturing the same

Stack packages are provided. The stack package includes a first chip and a second chip. The first chip includes a first chip body, first through electrodes penetrating the first chip body, and an insulation layer disposed on a bottom surface of the first chip body. The second chip includes a second chip body and bumps disposed on a top surface of the second chip body. The first and second chips are vertically stacked such that the bumps penetrate the insulation layer to pierce the first through electrodes and the top surface of the second chip body directly contacts the insulation layer. Related fabrication methods, electronic systems and memory cards are also provided.

A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

Semiconductor package using through-electrodes having voids

A stacked semiconductor package includes a first semiconductor package having a first semiconductor chip having a first pad and a through-hole passing through a the portion corresponding to the pad; a second semiconductor package disposed over the first semiconductor package, and including a second semiconductor chip having a second pad disposed at a portion corresponding to the first pad and blocking the through-hole; and a through-electrode disposed within the through-hole, and having a pillar shaped core supported by the second pad, a through-electrode unit disposed over a surface of the core and electrically connected with the second pad, a first metal layer interposed between the core and the through electrode unit, and a second metal layer interposed between an inner surface of the first semiconductor chip formed by the through-hole and the through-electrode unit.

Through-electrode, circuit board having a through-electrode, semiconductor package having a through-electrode, and stacked semiconductor package having the semiconductor chip or package having a through-electrode

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Icheon-si, South Korea

Han Jun Bae