Samsung Electronics Co., Ltd.

Namlab Ggmbh

Techno Semichem Co., Ltd.

Han-jin Lim

Seok-Woo Nam

Bong-hyun Kim

Ki-Vin Im

Youn-soo Kim

Jin-il Lee

Kwang-Hee Lee

Kyu-Ho Cho

Ki-chul Kim

Cha-young Yoo

Jae-Soon Lim

Kong-Soo Lee

Joon Hyuk Kim

Wan-Don Kim

Suk-Jin Chung

Hyun-jun Kim

Dong-Kak Lee

Won-Seok Yoo

Sung-Tae Kim

Young-Jin Kim

Dong-Chan Kim

Yong-jae Lee

Jae-young Ahn

Dong-Hyun Im

Hyun Uk Park

Wan-don Kim

In-seak Hwang

Cha-Young Yoo

Se-hoon Oh

Sang-Yeol Kang

Hong-suk Kim

Soo-jin Hong

Young-kuk Kim

Kyoung-Ryul Yoon

Sun-Min Moon

Jin-sun Lee

Soon-Gun Lee

Sung-Jin Kim

Dong-Suk Shin

Seok-Jun Won

Cheol-Woo Park

Ki-Hyun Hwang

Young-Seok Kim

Bon-Young Koo

Se-Jin Lee

Jae-hyoung Choi

Ji-Hoon Choi

Jong-myeong Lee

Jin-Yong Kim

Byung-Soo Kim

Seong-Hoon Jeong

Young-Geun Park

Jae-Jong Han

Jung-hee Chung

Uwe Schroeder

Ryong Ha

Hyun-Kwan Yu

Taek-Soo Jeon

Joon-Suk Lee

Se-Hoon Oh

Byoung-taek Lee

Jong-Bom Seo

Jung-Hwan Oh

Jeon-Il Lee

Chang-Won Choi

Jae-young Park

Seok-woo Nam

Jae-Sun Jung

In-Sang Jeon

Soon-yeon Park

Sung-Gil Kim

Jae-hong Seo

Jung-Hee Chung

Suk-jin Chung

Wook-Yeol Yi

Eun-Ae Cho

Sung-Je Choi

Phil-ouk Nam

Seul-ye Kim

Dong-Woon Shin

Han-mei Choi

Young-Sub Yu

Yoon-Goo Kang

Seung-Sik Chung

Beom-jong Kim

Seung-Ho Yoo

Yong-kuk Jeong

Gyung-hoon Hong

Woon-Ki Shin

Jin-Won Ma

Chang-Mu An

Chin-Moo Cho

Steve Knebel

A semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.

Semiconductor device including vertical channel layer and method of manufacturing the same

An electrode structure is disclosed. The electrode structure includes a first polysilicon layer doped with resistance adjustment impurities; a second polysilicon layer for adjusting grains, formed in the first polysilicon layer and doped with grain adjustment impurities; an ohmic metal layer formed on the first and second polysilicon layers; a barrier metal layer formed on the ohmic metal layer; and a metal layer formed on the barrier metal layer.

Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure

A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.

Methods of forming material layer

A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.

Vertical memory devices and methods of manufacturing the same

A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.

Method of manufacturing semiconductor device

A semiconductor device having a capacitor includes a substrate which has a transistor, a first insulating pattern which is formed on the substrate and does not overlap a first contact node formed in the substrate, a second insulating pattern which is formed on the substrate, does not overlap a second contact node formed in the substrate, and is separated from the first insulating pattern, a first lower electrode which is formed on part of the substrate and sidewalls of the first insulating pattern, a second lower electrode which is formed on part of the substrate and sidewalls of the second insulating pattern, a dielectric layer pattern which is formed on the first lower electrode and the second lower electrode, and an upper electrode which is formed on the dielectric layer pattern. Related fabrication methods are also discussed.

Semiconductor device having capacitor and method of fabricating the semiconductor device

Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.

Semiconductor devices including nanowire capacitors and fabricating methods thereof

Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Methods of fabricating semiconductor devices using nanowires

A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Methods of fabricating memory devices using wet etching and dry etching

A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

Semiconductor devices including diffusion barriers  with high electronegativity metals

A semiconductor device includes a substrate; a first inverter disposed on the substrate and receiving a voltage from any one of a bit line and a complementary bit line; a semiconductor layer disposed on the first inverter; and first and third switch devices disposed on the semiconductor layer and adjusting a threshold voltage of the first inverter to a voltage level of any one of the bit line and the complementary bit line.

Semiconductor device

A capacitor can include a crystallized metal oxide dielectric layer having a first dielectric constant and an amorphous metal oxide dielectric layer, on the crystallized metal oxide dielectric layer, where the amorphous metal oxide dielectric layer has a second dielectric constant that is less than the first dielectric constant and is greater than a dielectric constant of aluminum oxide.

Capacitors including amorphous dielectric layers and methods of forming the same

Provided is a semiconductor device and a method for fabricating the same. The semiconductor device includes an interlayer insulating layer formed on a semiconductor substrate, a metal contact plug penetrating the interlayer insulating layer, a cylindrical lower electrode formed on the metal contact plug and including a first metal and a trench, a supporter formed in the trench and including a second metal that is different from the first metal, a dielectric layer formed on the lower electrode and the supporter and an upper electrode formed on the dielectric layer.

Semiconductor device and method for fabricating the same

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Seoul, South Korea

Han-jin Lim