Electronics and Telecommunications Research Institute

Han Jin Cho

Kyung Soo Kim

Seong Mo Park

In San Jeon

Young Hwan Bae

Hyuk Joo Kim

In Gi Lim

Mi Young Lee

Hee Bum Jung

Seung Chul Kim

June Young Chang

Won Jong Kim

Jin Jong Cha

Jong Dae Kim

Jong Kee Kwon

Hyung-Il Park

Woo Seok Yang

Jin Ho Han

Soon Il Yeo

Ook Kim

Suk Ho Lee

Won Chul Song

Kyoung Seon Shin

Ig Kyun Kim

Jong Ryul Lee

Chang Jun Oh

Whan Woo Kim

Kwang Youb Lee

Guee Sang Lee

Ju Yeob Kim

Jun Young Chang

Tae Young Lim

A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

Switch block circuit in field programmable gate array

An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

Parity generating apparatus and map apparatus for turbo decoding

There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Distributed video coding apparatus and method capable of controlling encoding rate

Provided is an apparatus and method for performing intra prediction for an image decoder, in which by use of horizontal/vertical blocks adjacent to image data input from an external device, the intra prediction is performed in parallel with respect to 16&#xd7;16 luminance component and 4&#xd7;4 luminance component of the image data and then with respect to chrominance component, thereby maximizing efficiency of system to not only reduce execution time and hardware cost but also increase processing speed.

Apparatus and method for performing intra prediction for image decoder

An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.

On-chip network interfacing apparatus and method

Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2&#xd7;1 multiplexers connected in a matrix form consisting of rows and columns. The 2&#xd7;1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Crossbar switch architecture for multi-processor SoC platform

Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.

Apparatus for sequentially enabling and disabling multiple powers

In an apparatus for a TFCI mapping in a wireless communication mobile station, and a method thereof, the apparatus includes an encoding unit for encoding a TFCI transmitted from a main control unit as a CPU; a TFCI mapping unit for generating necessary control parameter and a TFCI code by using a signal encoded by the encoding unit and a signal transmitted from the CPU; and a CPU for controlling the encoding unit and the mapping unit.

Apparatus for TFCI mapping in wireless communication mobile station and method thereof

The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

Turbo decoder and its calculation methods having a state metric

The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.

Serial finite field multiplier

A modulator for an IMT-2000 synchronous mobile station in a digital telecommunication and modulating method thereof, and more particularly, an OCQPSK modulator using FIR filters, each for performing 1:4 interpolation operations for 4 input data and a modulating method thereof. The orthogonal complex quadrature phase shift keying OCQPSK modulating apparatus uses a 1-bit input FIR filter that includes pseudo noise spreading for bifurcating 1-bit data inputted from input channels and pseudo-spreading the bifurcated 1-bit data, an FIR filter for receiving the 1-bit data and performing a filtering operation for pulse shaping, a gain multiplying block for multiplying filtered data outputted from the FIR filter by a gain for respective channels, and a channel adder block for adding data outputted from the gain multiplying block to output I channel and Q channel signals.

OCQPSK modulator and modulating method using 1-bit input FIR filter

An apparatus for motion estimation with control part implemented by state transition diagram without adding delay circuits to processing elements, and capable of maintaining a regular data flow and easily implementing hardware to improve a power consume and speed is disclosed. The apparatus comprises a first and second storage parts for storing data; a measurement part for finding an absolute difference between the data; a step decision part for determining a minimum value; and a control part implemented by state transition diagram.

Apparatus for motion estimation with control part implemented by state transition diagram

The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.

Low offset automatic frequency tuning circuits for continuous-time filter

An error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, includes a first storage device for temporarily storing the run representing the number of zeros ('0's) in the compressed image data and an EOB signal externally inputted, a selection signal generator for generating a first and a second selection signal in response to the EOB signal supplied from the first storage device, a first selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the first selection signal, a second selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the second selection signal, a reference value generator for generating a reference value based on the output signal of the first selection circuit according to an operation control signal externally inputted, accumulator for accumulating the output of the second selection circuit based on the feedback signal from a second storage device, the second storage device temporarily storing the output of the accumulator, and an error detector for detecting the errors based on the reference value and the output of the second storage device.

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Daejeon, South Korea

Han Jin Cho