Siliconware Precision Industries Co., Ltd.

Han-Hung Chen

Chang-Fu Lin

Rung-Jeng Lin

Kuo-Hua Yu

Fu-Tang Huang

Chun-Yi Huang

Shi-Min Zhou

Chee-Key Chung

Yuan-Hung Hsu

Yu-Min Lo

The present disclosure provides a package stack structure and a method for manufacturing the same. The method is characterized by stacking coreless circuit portions on the board of an electronic component to reduce the overall thickness of the package stack structure.

Package stack structure and method for manufacturing the same

An electronic package and a method for fabricating the same are provided. The method includes stacking an antenna board on a circuit board, and disposing between the antenna board and the circuit board a supporting body securing the antenna board and the circuit board. As such, during a packaging process, the distance between the antenna board and the circuit board is kept unchanged due to the supporting body, thus ensuring that the antenna board operates properly and improving the product yield.

Electronic package and method for fabricating the same

An electronic package is disclosed. An antenna board is stacked on a circuit board. A frame is formed on the circuit board. A supporter disposed between the antenna board and the circuit board is secured in the frame. In a packaging process, the frame ensures that the antenna board and the circuit board are separated at a distance that complies with a requirement, and that the antenna function of the antenna board can function normally.

Electronic package

An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.

Method for fabricating electronic package

The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.

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Taichung, Taiwan

Han-Hung Chen