Qualcomm Incorporated

Han Huang

Marta Karczewicz

Wei-Jung Chien

Vadim Seregin

Chun-Chi Chen

Zhi Zhang

Yao-Jen Chang

Yan Zhang

Yu Han

Kevin Pascal Andre Reuze

Luong Pham Van

Geert Van Der Auwera

Cheng-Teh Hsieh

Jianle Chen

Adarsh Krishnan Ramasubramonian

Hongtao Wang

Bappaditya Ray

Yung-Hsuan Chao

Muhammed Zeyd Coban

Po-Han Lin

Chao-Hsiung Hung

Kevin Reuze

Encoding and decoding video data using an affine decoder side motion vector derivation (DMVR) mode includes receiving a block of video data to be decoded using the affine DMVR mode, and dividing the block into a plurality of subblocks. A video encoder and video decoder may determine a final offset for the affine DMVR mode using a first subset of the plurality of subblocks. The video encoder and decoder may code the block of video data using the final offset to generate a coded block of video data.

Methods of subblock skipping for affine motion search for video coding

An example device for decoding video data includes one or more processors configured to: determine that a first weight and a second weight are specified for a bi-prediction mode predicted current block of video data; determine whether the current block is to be predicted using multi-hypothesis prediction (MHP) mode with the bi-prediction mode as a base mode; in response to determining that the current block is to be predicted using the MHP mode with the bi-prediction mode as the base mode, determine an additional inter-prediction mode of the MHP mode; generate a first prediction block according to the bi-prediction mode; generate a second prediction block according to the additional inter-prediction mode; generate a final prediction block for the current block according to the MHP mode using the first prediction block and the second prediction block; and decode the current block using the final prediction block.

Multiple hypothesis prediction for video coding

An example device for coding video data includes memory configured to store the video data and one or more processors communicatively coupled to the memory. The one or more processors are configured to reduce a bit length of one or more input variables for a linear regression operation to generate one or more reduced bit length input variables, the input variables including at least one of a) one or more delta coordinates, b) one or more delta motion vectors, or c) a value representing a number of subblocks. The one or more processors are configured to perform the linear regression operation and derive an affine motion model based on the performing the linear regression on the one or more reduced bit length input variables. The one or more processors are configured to code a current block of the video data based on the affine motion model.

Bit-length control for linear regression-based affine merge candidate derivation

A video coder is configured to construct a merge candidate list of merge candidates, wherein the merge candidate list has N1 candidates, N1 being a positive integer value, reorder the merge candidates in the merge candidate list to create a reordered merge candidate list, reduce the reordered merge candidate list to create an output merge candidate list, wherein the output merge candidate list has N2 candidates, wherein N2 is less than N1, and code a block of video data using the output merge candidate list.

Merge candidate reordering in video coding

A method for coding a block of video data using affine mode includes determining a refined affine model for the current block of video data from a linear regression process using a base motion vector field and a guidance motion vector field as inputs to the linear regression process. The method further includes determining affine merge candidates for the current block using the refined affine model, and coding the current block of video data using the affine merge candidates.

Derivation of affine merge candidates with linear regression for video coding

A device for decoding video data includes a memory configured to store video data; and one or more processors implemented in circuitry and configured to: determine that a boundary block of a picture of the video data is bi-directional inter-predicted using a first motion vector and a second motion vector, the boundary block having an edge that touches an edge of the picture; decode the picture, including decoding the boundary block; form a first intermediate padding block using the first motion vector; form a second intermediate padding block using the second motion vector; form a padding block using the first intermediate padding block and the second intermediate padding block; and assign padding values of the padding block to a padding region of the picture neighboring the boundary block on an opposite side of the edge of the picture.

Bi-directional prediction boundary pixel padding with out-of-picture-boundary motion vectors

A video decoder may be configured to generate a first ordering of reference pictures in a reference picture list for a first block of a slice, wherein generating the first ordering of the reference pictures for the first block comprises assigning indexes to the reference pictures; and generate a second ordering of the reference pictures in the reference picture list for a second block of the slice based on an adaptive reference picture reordering process, wherein the first ordering is different than the second ordering and generating the second ordering of reference pictures for the second block comprises assigning at least some of the indexes to different reference pictures than in the first ordering; decode the first block using the first ordering of the reference pictures; and decode the second block using the second ordering of the reference pictures.

Block level reference pictures adaptation for video coding

A video decoder may be configured to determine a motion vector and a motion vector precision for a current block; identify a current block template within the current picture; search within a search area for a final reference block template that corresponds to the current block template, wherein to search within the search area, the one or more processors are further configured to: identify an initial reference block template based on the motion vector, search other reference block templates around the initial reference block template using a step size that is set to an initial step size, and iteratively reduce the step size from the initial step size until the step size is set to a final step size that equals the motion vector precision; determine a prediction block for the current block based on the final reference block template.

Template matching in video coding

An example device for decoding video data includes one or more processors configured to determine merge mode information for a current block, the merge mode information indicating that motion information for a current block is to be predicted using a first predictor motion vector and a second predictor motion vector; determine a first motion vector difference (MVD) for the first predictor motion vector and a second MVD for the second predictor motion vector, the second MVD being different than the first MVD; form a first motion vector equaling a combination of the first motion vector predictor and the first MVD; form a second motion vector equaling a combination of the second motion vector predictor and the second MVD; generate a prediction block using the first motion vector and the second motion vector; and decode the current block using the prediction block.

MMVD merge mode with asymmetric motion vector difference

A video decoder can be configured to determine that a current block of the video data is coded in a bi-prediction inter mode; receive a first syntax element identifying a motion vector predictor from a first candidate list of motion vector predictors; receive a second syntax element identifying a motion vector difference; determine a first motion vector for the current block based on the motion vector predictor and the motion vector difference; determine a second motion vector for the current block from a second list of candidate motion vector predictors based on bilateral matching; and determine a prediction block for the current block using the first motion vector and the second motion vector.

Hybrid inter bi-prediction in video coding

A method of decoding video data comprising parsing a sub-prediction unit motion flag from received encoded video data, deriving a list of sub-prediction unit level motion prediction candidates if the sub-prediction unit motion flag is active, deriving a list of prediction unit level motion prediction candidates if the sub-prediction unit motion flag is not active, and decoding the encoded video data using a selected motion vector predictor.

Signaling sub-prediction unit motion vector predictor

A device for decoding video data comprises one or more processors configured to: obtain a syntax element from a bitstream that includes an encoded representation of the video data; determine, based on the syntax element, that a template-matching tool is enabled; based on the template-matching tool being enabled, applying the template-matching tool to generate a prediction block for a current coding unit (CU) of the video data; and reconstruct the current CU based on the prediction block for the current CU.

High-level syntax control flags for template matching-related coding tools in video coding

Example techniques and devices are disclosed for coding video data. An example device includes memory configured to store the video data and one or more processors implemented in circuitry and communicatively coupled to the memory. The one or more processors are configured to determine that multiple-hypothesis prediction (MHP) is enabled. The one or more processors are configured to, based on determining that MHP is enabled, determine a maximum number of merge candidates for a MHP merge candidate list. The one or more processors are configured to, based on the maximum number of merge candidates for the MHP merge candidate list, determine the MHP merge candidate list. The one or more processors are configured to code the video data based on the MHP merge candidate list.

Methods for adaptive signaling of maximum number of merge candidates in multiple hypothesis prediction

Systems and techniques are provided for coding video data. In some examples, a process may include obtaining a first plurality of prediction candidates associated with video data. The process may further include determining a first group of prediction candidates at least in part by applying a first grouping method to the first plurality of prediction candidates. The process may include reordering the first group of prediction candidates and selecting a first merge candidate from the reordered first group of prediction candidates. The process may further include adding the first merge candidate to a candidate list.

Motion vector (MV) candidate reordering

An example device for decoding video data includes one or more processors configured to: generate a first prediction block for a current block of video data using a base inter-prediction mode; code a merge mode syntax element for a second prediction block representing an additional prediction hypothesis, the merge mode syntax element indicating whether motion information for the second prediction block is coded using merge mode; code the motion information for the second prediction block according to the merge mode syntax element, wherein to code the motion information, the one or more processors are configured to form a merge candidate list including merge candidates representing respective sets of uni-prediction motion information; generate the second prediction block for the current block of video data using the motion information; form a multi-hypothesis prediction block from the first and second prediction blocks; and decode the current block using the multi-hypothesis prediction block.

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San Diego, CA, United States of America

Han Huang