Altera Corporation

Han Hua Leong

David Wolk Mendel

Peter Schepers

Suresh Gordhanlal Andani

Yanjing Ke

Siew Leong Lam

Seng Kuan Yeow

Ru Yin Ng

Si Xing Saw

Keen Yew Loke

Chiang Wei Lee

Geok Sun Chong

The present disclosure provides a link assist capability that may be added to a compiled design that includes a transceiver. The transceiver with the link assist capability may be dynamically reconfigured to operate in a link assist mode, which is a diagnostic and test mode. The link assist mode may interact with a HSSI link partner, or a design software tool, or a user-defined program. The link assist mode may also facilitate remote debugging. One embodiment relates to an apparatus for serial interface link assist. Another embodiment relates to a method of dynamic reconfiguration of transceiver settings. Another embodiment relates to a method of tuning a bidirectional serial link. Other features, aspects and embodiments are also disclosed.

Methods and apparatus for high-speed serial interface link assist

Circuits and methods are disclosed for low-skew bonding of a plurality of data channels into a multi-lane data channel. In one embodiment, phase-measuring first-in first-out buffer circuits buffer pre-buffer parallel data signals and generate phase-measurement signals. A channel-bonding control circuit receives the phase-measurement signals and generates bit-slip control signals. Transmission bit-slip circuits slip integer numbers of bits based on the bit-slip control signals. Bypass registers may be used when the integer number of bits is greater or equal to the parallel width of a lane. In another embodiment, the channel-bonding control circuit receives the phase-measurement signals from the phase-measuring FIFO buffer circuits and generates clock-slip control signals. Clock slip circuits controllably slip parallel clock signals by integer numbers of unit intervals of a serial clock signal. Various other aspects, features, and embodiments are also disclosed.

Low-skew channel bonding using phase-measuring FIFO buffer

A control system controls First-In First-Out (FIFO) settings of a receiving system. The control system includes a FIFO settings controller that receives a first signal indicative of a first frequency of data received by the receiving system. The FIFO settings controller receives a second signal indicative of a second frequency of a clock that reads the data received by the receiving system. The FIFO settings controller determines a difference (e.g., a parts-per-million (PPM) difference) between the first frequency and the second frequency. The FIFO settings controller sends a third signal indicative of instructions to adjust FIFO configuration settings based on the PPM difference.

Adaptive rate-matching first-in first-out (FIFO) system

An integrated circuit may include multiple circuit blocks, each with an associated latency value. As an example, transceiver circuitry in an integrated circuit may receive different data packets and circuit blocks in the transceiver circuitry may have different latency values depending on the data packets received. The integrated circuit may further include latency computation circuitry that receives the different latency values from the multiple circuit blocks. The latency computation circuitry may accordingly output a total latency value for the multiple circuit blocks in the integrated circuit based on the received latency values.

Latency computation circuitry

Circuits and techniques for operating an integrated circuit (IC) are disclosed. A disclosed circuit includes a divider circuit that is operable to receive a first signal at a first speed and output a second signal at a second speed based on the first signal. A recovery circuit is coupled to the divider circuit. The recovery circuit is operable to determine the frequency of the second signal and is further operable to generate a first ready signal and a recovered clock signal based on the second signal. A phase aligner circuit, operable to align a phase of the second signal with a phase of the recovered clocks signal based on the first ready signal, is coupled to the recovery circuit.

Integrated circuit (IC) clocking techniques

Transceiver circuitry may include a storage element that receives data signals from an external element, an alignment detector circuit, and a register. The storage element has a write clock terminal that receives a channel clock signal and a read clock terminal that receives another channel clock signal. The alignment detector circuit is adapted to generate an asserted ready signal when a predefined pattern is detected in the received data signals. The register receives an output signal from the storage element and outputs the output signal based on the asserted ready signal that is generated by the alignment detector circuit. The register may be clocked by the same channel clock signal that is received at the read clock terminal of the storage element.

Methods and apparatus for aligning signals in transceiver circuitry

Techniques and mechanisms determine latencies of transmitters of transceivers and use the determined latencies to adjust latencies of the transmitters. For example, a test pattern may be used to determine a first transmitter has a higher latency than a second transmitter. The second transmitter may be provided data indicating a delay to increase its latency such that it matches the first transmitter.

Growing community of inventors

Butterworth, Malaysia

Han Hua Leong