Hyundai Electronics Industries Co. Ltd.

Han Heung Kim

Suk Joong Lee

Mun Weon Ahn

A microprocessor of a superscalar structure having a datapath, a data cache, a bus unit and first and second pipelines includes a write buffer equipped in the bus unit and a write back buffer in the data cache to reduce write cycles. The write buffer receives data of a burst write cycle from the write back buffer and data of a single write cycle from the datapath. The write buffer in the microprocessor allows data to be written in the write buffer and then to be written in the external memory when the microprocessor is available for performing an external cycle. The processor includes a state machine to control the write buffer and also includes one write buffer for each of the first and second pipelines in order to diminish the write cycles. The write buffers also include a bit block which indicates whether information in the write buffer is written by a cache miss or a hit in a line having a shared state. The state machine includes idle, request, service, backoff (BOFF) and update states in controlling write cycle progression in a pipeline.

Superscalar processor employing a high performance write back buffer controlled by a state machine to reduce write cycles

An apparatus serves to map internal registers into I/O addresses to select an internal register and perform read and write operations in the I/O address space of the PCMCIA host adapter, using the index mapping mechanism. The apparatus according to the present invention includes a plurality of internal registers for storing an input data, being arranged in the PCMCIA card; a plurality of first AND gates for producing a first control signal in response to index signals from an index register; a plurality of second AND gates for producing a register enabling signal in response to the first control signal and a data write signal from CPU; and a plurality of AND gates means for producing a third control signal outputting data stored in the internal register.

Apparatus for mapping memory PCMCIA cards into I/O window address space

A bus interface unit has an arbitrating unit, in response to cycle requests received from internal devices of a processor and a resumption request, for determining an internal device having the highest priority and generating a cycle acknowledgment signal representing thereof; a queue input multiplexing unit, in response to the cycle acknowledgment signal, for selecting cycle queue data from the determined internal device to generate selected cycle queue data; a cycle queue storing unit for storing the selected cycle queue data and state information under; and a queue controlling unit for controlling the cycle queue storing unit to store the selected cycle queue data and the state information under the condition that a back-off condition occurs, and for resuming a cycle under the condition that the back-off condition is cleared by using the stored selected cycle queue data based on the state information to provide the resumption request to the arbitrating unit.

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Kyoungki-do, South Korea

Han Heung Kim