Imec Vzw

Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Katholieke Universiteit Leuven

Han Chung Lin

Boon Teik Chan

Jan F Van Houdt

Marc A Meuris

Hanns Christoph Adelmann

Jean-Francois De Marneffe

Wei-e Wang

Daniil Marinov

Inge Asselberghs

Laura Nyns

Tsvetan Ivanov

Dennis Van Dorp

Tsvetan Ivanonv

In a first aspect, the present disclosure relates to a method for removing an organic sacrificial material from a 2D material, comprising: providing a target substrate having thereon the 2D material and a layer of the organic sacrificial material over the 2D material, infiltrating the organic sacrificial material with a metal or ceramic material, and removing the organic sacrificial material.

Removing an organic sacrificial material from a two-dimensional material

The disclosed technology generally relates to methods of fabricating a semiconductor device, and more particularly to methods of fabricating a ferroelectric field-effect transistor (FeFET). According to one aspect, a method of fabricating a FeFET includes forming a layer stack on a gate structure, wherein forming the layer stack comprises a ferroelectric layer followed by forming a sacrificial stressor layer. The method additionally includes heat-treating the layer stack to cause a phase transition in the ferroelectric layer. The method additionally includes, subsequent to the heat treatment, replacing the sacrificial stressor layer with a two-dimensional (2D) material channel layer. The method further includes forming a source contact and a drain contact contacting the 2D material channel layer.

Method of fabricating ferroelectric field-effect transistor

A semiconductor structure comprises a substrate including a III-V material, and a high-k interfacial layer overlaying the substrate. The interfacial layer includes a rare earth aluminate. The present disclosure also relates to an n-type FET device comprising the same, and a method for manufacturing the same.

III-V semiconductor device with interfacial layer

A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.

Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device

Growing community of inventors

Leuven, Belgium

Han Chung Lin