Taiwan Semiconductor Manufacturing Comp. Ltd.

Han-Chung Lin

Hua-Chou Tseng

Yung-Chih Tsai

Chung-Yi Lin

Yen-Sen Wang

A method of the present disclosure includes receiving a design layout; performing routing to the design layout to obtain a routed layout including an interconnect structure including a first metal layer, a second metal layer over the first metal layer, a third metal layer over the second metal layer, and a plurality of functional vias; performing optical proximity correction (OPC) operations to the routed layout to obtain an OPC'ed layout; and modifying the OPC'ed layout to obtain a modified layout. The modifying of the routed layout includes inserting a first plurality of dummy vias between the first metal layer and the second metal layer to avoid horizontal bridging between two adjacent metal lines in the first metal layer, and inserting a second plurality of dummy vias between the second metal layer and the third metal layer to avoid vertical coupling to the first plurality of dummy vias.

Charging prevention method and structure

A method for semiconductor devices on a substrate includes using gate structures which serve as active gate structures in a MOSFET region, as dummy gate structures in a JFET region of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments, thereby forming an accurately dimensioned transistor channel.

Junction FET semiconductor device with dummy mask structures for improved dimension control and method for forming the same

The present disclosure provides a semiconductor device. The semiconductor device includes a first doped region and a second doped region both formed in a substrate. The first and second doped regions are oppositely doped. The semiconductor device includes a first gate formed over the substrate. The first gate overlies a portion of the first doped region and a portion of the second doped region. The semiconductor device includes a second gate formed over the substrate. The second gate overlies a different portion of the second doped region. The semiconductor device includes a first voltage source that provides a first voltage to the second gate. The semiconductor device includes a second voltage source that provides a second voltage to the second doped region. The first and second voltages are different from each other.

Dummy gate for a high voltage transistor device

A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate structures in the JFET portion of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments. The transistor channel is therefore accurately dimensioned.

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Hsinchu, Taiwan

Han-Chung Lin