Au Optronics Corporation

So Bright Electronics Co., Ltd.

Han-Chung Lai

Ta-Wen Liao

Wen-Chih Chen

Tung-Yu Chen

Chun-Hao Su

Han-Tu Lin

Hsin-Hung Chen

Shu-Chin Lee

Chun-Chih Lai

Yen-Hua Hsu

Po-Wen Teng

Jui-Hsiang Chen

Nan-Huei Jiang

A mask including patterned structures arranged sequentially along a predetermined direction and a peripheral area surrounding the patterned structures is provided. Each of the patterned structures includes an opening portion and a thinning portion surrounding the opening portion. The opening portion has through holes arranged in a matrix. An outline of the thinning portion has two side edges opposite to each other substantially parallel to the predetermined direction. The thinning portion is defined by an area demarked by the outline of the thinning portion and an outline of the opening portion. A thickness of the thinning portion is thinner than a thickness of the peripheral area.

Mask

A LED package structure includes a substrate unit, a light-emitting unit and a package unit. The substrate unit includes two lead frames, and light-emitting unit including a LED chip electrically connected between the two lead frames. The package unit includes a light-transmitting package body enclosing the light-emitting unit and one part of each lead frame and a lens body integrated with the light-transmitting package body, and another part of each lead frame is exposed from the light-transmitting package body. Therefore, light beams generated by the LED chip pass through the lens body to project a cross light pattern on a plane, the cross light pattern has a concentrated cross light shape and a scattered light shape surrounding the concentrated cross light shape, the luminous intensity of the concentrated cross light shape is substantially the same and larger than the luminous intensity of the scattered light shape.

LED package structure

A method is used to prevent unwanted electrical contacts between various electrically conducting surfaces and lines in a display panel due to an n+ a-Si residue and/or ITO debris. The method provides a clearing pattern including at least a cleared area in the passivation layer for preventing the residue or debris from locating at the cleared area. As such, if an n+ a-Si residue happens to be deposited under the passivation layer, the part of the residue located in the cleared area is removed by an a-Si selective etching process, for example. Furthermore, with the cleared area, ITO debris deposited on the section of the dielectric layer deposited on the signal line can be electrically isolated from the electrode.

Residue isolation process in TFT LCD fabrication

A thin film transistor array comprising a substrate, a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors, a plurality of common lines, a plurality of top electrodes, a plurality of connection lines and a plurality of pixel electrodes is provided. Wherein, each thin film transistor is disposed in one of the pixel areas and driven through the corresponding scan line and data line. Each thin film transistor includes a gate, a source and a drain. The drain of the thin film transistor is electrically connected to the corresponding top electrode by the corresponding connection line. Besides, the drain of the thin film transistor is electrically connected to the pixel electrode, and a portion of the connection line is not covered by the pixel electrode.

Method for repairing thin film transistor array by welding a top electrode to a common line

A thin film transistor array substrate including a substrate, scan lines, data lines, thin film transistors, pixel electrodes, common lines and a patterned upper electrode is provided. The scan lines and the data lines are disposed over the substrate to define pixel areas. Each thin film transistor is disposed within one of the pixel areas and is driven by one of the scan lines and data lines. Each pixel electrode is disposed within one of the pixel areas and is electrically connected to one of the thin film transistors. Common lines are disposed over the substrate such that a portion area of each pixel electrode is located above one of the common lines. The pattern upper electrode includes sub-upper electrodes disposed between the pixel electrode and the common line. The sub-upper electrodes are electrically connected to the pixel electrodes for coupling with the common lines to form a storage capacitor.

Thin film transistor array substrate having particular pixel electrode and patterned upper electrode

A fabrication method of a multi-domain vertical alignment pixel structure includes providing a substrate, forming a gate on the substrate, and forming an insulating layer on the substrate. A channel layer and a semiconductor layer are formed on the insulating layer. A source, a drain, and a capacitor-coupling electrode are formed. A passivation layer is formed to cover the source, the drain, a part of the channel layer, and a part of the semiconductor layer. A via hole is formed in the passivation layer to expose the drain, and a trench is formed in the passivation layer and the insulating layer. A lateral etched groove on the sidewall of the trench is formed to expose the side edge of the semiconductor layer. A first pixel electrode and a second pixel electrode are formed on the passivation layer at both sides of the trench, respectively.

Fabrication method of multi-domain vertical alignment pixel structure

An active matrix substrate including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units is provide. All of the scan lines, the data lines, the pixel units are disposed on the substrate. Each of the pixel units is electrically connected with the corresponding scan line and data line. In addition, at least a part of the pixel units further includes a plurality of active devices and a pixel electrode. The active devices are respectively electrically connected with the corresponding scan lines and data lines and the pixel unit is electrically connected with one of the active devices. In summary, each of the pixel units of the active matrix substrate provided by the invention includes more than one active device. When an active device is damaged under normal operation, another active device may be employed for repairing the pixel unit.

Active matrix substrate and repair method of pixel unit

Pixel structure and TFT array drain connected to pixel electrode without connection line from drain to top electrode therebetween

An active matrix substrate including a substrate, a plurality of pixel units, a plurality of driving lines, an electron static discharge (ESD) protection circuit and a floating line is provided. The substrate has an active region and a peripheral region connected with the active region. The pixel units are arranged in a matrix in the active region. The driving lines electrically connected to the pixels are disposed in the active region and the peripheral region. The ESD protection circuit and the floating line are disposed in the peripheral region of the substrate. The ESD protection circuit is electrically connected to the driving lines. The ESD protection circuit includes an outer short ring (OSR) and an inner short ring (ISR) disposed between the pixel units and the OSR. The floating line is located beside the outer driving line.

Active matrix substrate and repairing method thereof

A method for repairing a storage capacitor on gate or a storage capacitor on common line is described. A portion of each pixel electrode is disposed above a scan line or a common line. An upper electrode is disposed between the pixel electrode and the corresponding scan line or the common line. The pixel electrode and the upper electrode are electrically connected. A defective capacitor is formed when a particle/defect is produced between the upper electrode and the common line or the scan line. The method of repairing the defective capacitor includes removing a portion of the pixel electrode corresponding to the upper electrode of a defective storage capacitor and electrically isolating the upper electrode and the corresponding pixel electrode of the defective storage capacitor. The upper electrode and the scan line or the common line of the defective capacitor are welded together.

Repairing method of a thin film transistor array substrate

An active matrix substrate including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel units is provide. All of the scan lines, the data lines, the pixel units are disposed on the substrate. Each of the pixel units is electrically connected with the corresponding scan line and data line. In addition, at least a part of the pixel units further includes a plurality of active units and a pixel electrode. The active devices are respectively electrically connected with the corresponding scan lines and data lines and the pixel unit is electrically connected with one of the active devices. In summary, each of the pixel units of the active matrix substrate provided by the invention includes more than one active device. When an active device is damaged under normal operation, another active device may be employed for repairing the pixel unit.

A method of manufacturing a pixel structure controlled by a data line and a scan line is provided. A gate electrode electrically coupled to the scan line is formed on a substrate and a first dielectric layer covering the scan line and the gate electrode is formed. A first and a second semiconductor layer are formed on the dielectric layer and a source/drain and a patterned conductor layer are formed. A second dielectric layer is formed on the substrate to cover the data line, the resistance line and the source/drain. A first pixel electrode and a second pixel electrode are formed on the second dielectric layer and these two pixel electrodes are separated from each other; wherein the first pixel electrode is electrically connected to one of the source/drain while the second pixel electrode is electrically connected to another of the source/drain through the resistance wire.

Method of manufacturing pixel structure

A thin film transistor array includes a substrate, scan lines, data lines, thin film transistors, upper electrodes and pixel electrodes. The scan lines and the data lines are disposed on the substrate to define pixel areas on the substrate. The thin film transistors are disposed inside corresponding pixel areas and are driven through corresponding scan line and data lines. The upper electrodes are disposed within various pixel areas above the scan lines. The upper electrode has a protrusion protruding beyond the edge of a corresponding scan line. The pixel electrode is disposed within a corresponding pixel area and electrically connected to a corresponding thin film transistor and upper electrode, wherein each pixel electrode has at least a slit formed therein, the slit has an end portion near the corresponding scan line, and the end portion is completely shielded by the protrusion of the corresponding upper electrode.

Thin film transistor array

A multi-domain vertical alignment pixel structure including an active device, a passivation layer, a first pixel electrode, a second pixel electrode, a capacitor-coupling electrode and a semiconductor layer is provided. The active device is disposed on the substrate and has an insulating layer, the passivation layer covers the active device and a part of the insulating layer, the first pixel electrode and second pixel electrode are disposed on the passivation layer and electrically insulated from each other. In addition, the capacitor-coupling electrode is disposed between the second pixel electrode and the substrate. The semiconductor layer is disposed between the insulating layer and the passivation layer, wherein the insulating layer and the passivation layer have a trench and a lateral etched groove located on the sidewall of the trench, and the lateral etched groove exposes the side edge of the semiconductor layer.

Multi-domain vertical alignment pixel structure

A flat panel display and fabrication method thereof. The present invention uses four etching processes to define a second conducting layer, a doped semiconductor layer and a semiconductor layer. The first etching process is a wet etching using a first resist layer to etch the second conducting layer. The second etching process is executed with an etchant comprising oxygen to etch the doped semiconductor layer and the semiconductor layer, and the first resist layer undergoes ashing during etching so as to become a second resist layer with a channel pattern. The third etching process is another wet etching, and the second conducting layer is etched again using the second resist layer as the etching mask. The fourth etching process is executed to dry etch the doped semiconductor layer using the second resist layer as the etching mask.

Growing community of inventors

Taoyuan Hsien, Taiwan

Han-Chung Lai