Taiwan Semiconductor Manufacturing Comp. Ltd.

Han-Chin Chiu

Chi-Ming Chen

Cheng-Yuan Tsai

Chung-Yi Yu

King-Yuen Wong

Chen-Hao Chiang

Chia-Shiung Tsai

Po-Chun Liu

Fu-Wei Yao

Ming-Wei Tsai

Hsing-Lien Lin

Sheng-De Liu

Xiaomeng Chen

Yao-Chung Chang

Yu-Syuan Lin

Chun-Wen Cheng

Chun-Ren Cheng

Yao-Wen Chang

Yi-Hsien Chang

Yi Heng Tsai

Kai-Chih Liang

Wei-Cheng Shen

Tzu-Heng Wu

Cheng-Te Lee

Trinh Hai Dang

Wen-Yuan Hsieh

A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Method of implanting dopants into a group III-nitride structure and device formed

The present disclosure, in some embodiments, relates to a semiconductor device. The semiconductor device includes an electron supply layer that is disposed over an upper surface of a semiconductor material and that is laterally arranged between a first conductive terminal and a second conductive terminal. A III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer is disposed over the III-N semiconductor material, along a side of the III-N semiconductor material, and over the electron supply layer. An insulating material is arranged over the passivation layer and along opposing sidewalls of the second conductive terminal, and a gate structure is disposed over the passivation layer. The passivation layer has an uppermost surface that is directly coupled to a sidewall of the passivation layer. The insulating material extends along the sidewall of the passivation layer.

HEMT-compatible lateral rectifier structure

A semiconductor device includes a compound semiconductor layer comprising a III-V material; a first layer on the compound semiconductor layer and comprising oxygen, nitrogen, and a material included in the compound semiconductor layer; a second layer over the first layer, wherein at least a portion of the second layer comprises a single crystalline structure or a polycrystalline structure; a dielectric layer over the second layer; and a source/drain electrode extending through the dielectric layer, the second layer, and the first layer and into the compound semiconductor layer.

Surface treatment and passivation for high electron mobility transistors

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.

Sidewall passivation for HEMT devices

The present disclosure, in some embodiments, relates to a method of forming a transistor device. The method may be performed by forming an anode and a cathode over an electron supply layer disposed on a semiconductor material. A doped III-N semiconductor material is formed over the electron supply layer, and an insulating material is formed over the electron supply layer and the doped III-N semiconductor material. The insulating material continuously extends from over the anode to over the cathode. The insulating material is patterned to form sidewalls of the insulating material that define an opening over the doped III-N semiconductor material. A gate structure is formed directly between the sidewalls of the insulating material and over the doped III-N semiconductor material.

A semiconductor device includes a compound semiconductor layer, an oxide layer over and contacting the compound semiconductor layer, a nitride layer over and contacting the oxide layer, and a dielectric layer over and contacting the nitride layer. At least a portion of the oxide layer comprises a first crystalline structure. At least a portion of the nitride layer comprises a second crystalline structure.

The present disclosure, in some embodiments relates to a semiconductor device. The semiconductor device includes a layer of semiconductor material disposed over a substrate and an electron supply layer disposed over the layer of semiconductor material between an anode terminal and a cathode terminal. A layer of III-N (III-nitride) semiconductor material is disposed over the electron supply layer. A passivation layer contacts an upper surface of the electron supply layer and further contacts an upper surface and a sidewall of the layer of III-N semiconductor material. A gate structure is separated from the layer of III-N semiconductor material by the passivation layer.

Some embodiments of the present disclosure relate to a HEMT. The HEMT includes a heterojunction structure having a second III/V semiconductor layer arranged over a first III/V semiconductor layer. Source and drain regions are arranged over the substrate and spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. A first passivation layer is disposed about sidewalls of the gate structure and extending over an upper surface of the gate structure, wherein the first passivation layer is made of a III-V material. A second passivation layer overlies the first passivation layer and made of a material composition different from a material composition of the first passivation layer. The second passivation layer has a thickness greater than that of the first passivation layer.

The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a laminated capacitor dielectric layer including alternating layers of high-k dielectric material and high-energy band gap material, and a method of formation. In some embodiments, the MIM capacitor has a laminated capacitor dielectric layer disposed over a capacitor bottom metal layer. The laminated capacitor dielectric layer includes a first layer of a first dielectric material, a second layer of a second dielectric material disposed on top of the first layer, a third layer of a third dielectric material disposed on top of the second layer, and a fourth layer of a fourth dielectric material disposed on top of the third layer. The first and third dielectric materials have a differing capacitance and band gap energy as compared to the second and fourth dielectric materials. A capacitor top metal layer is disposed over the laminated capacitor dielectric layer.

MIM device with laminated dielectric layers

Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a first III/V semiconductor layer, and a second III/V semiconductor layer arranged over the first III/V semiconductor layer. Source and drain regions are arranged over the second III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.

A method includes forming a first III-V compound layer over a substrate; forming a second III-V compound layer over the first III-V compound layer, wherein the first and second III-V compound layers include different materials; forming a first crystalline oxide layer over the second III-V compound layer; and forming a first crystalline interfacial layer over the first crystalline oxide layer.

A semiconductor structure includes a semiconductive substrate having a top surface, a III-V compound layer covering the top surface, and a passivation layer having a lower portion and an upper portion, both comprising at least one of oxide and nitride over the III-V compound layer. The semiconductor structure also includes an etch stop layer between the lower portion and the upper portion of the passivation layer, and a gate stack penetrating through the etch stop layer and landing on the lower portion of the passivation layer. The gate stack is surrounded by the etch stop layer.

High-electron-mobility transistor (HEMT) structure capable of protecting a III-V compound layer and manufacturing method thereof

A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The HEMT includes a first III-V compound layer having a first band gap and a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap. The HEMT further includes a first oxide layer over the second III-V compound layer; a first interfacial layer over the first oxide layer; and a passivation layer over the first interfacial layer.

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Kaohsiung, Taiwan

Han-Chin Chiu