General Electric Company

Hamza Yilmaz

Mike F Chang

King Owyang

Robert G Hodgins

Robert S Wrathall

George L Gauffreau

An isolation structure for isolating a pilot device from the main device of a monolithic semiconductor device. The isolation structure comprises a pair of spaced isolation channels separating the pilot device from the main device. An electrode insulatively disposed over the region between the two isolation channels is shorted by a metallization layer to the isolation channel closest to the pilot device. In this manner, parasitic transistor turn on of the isolation structure is prevented.

Isolation for transistor devices having a pilot structure

An insulated gate device includes at least one cell having base and emitter region surfaces disposed in ohmic contact with a metallic emitter electrode. The cell is constructed to provide a larger ratio of base region surface area to emitter region surface area in contact with the emitter electrode than is found in the prior art. The cell is further constructed to provide paths for reverse current flow from a drift region through the base region and to the emitter electrode; these paths being spaced form the cell's emitter-base junction.

Insulated gate device

During fabrication of an insulated gate device, a drain-forming dopant having a relatively low diffusion coefficient is implanted along a substrate surface which overlaps the boundary between a to-be-formed vertical drain region and a to-be-formed adjacent channel region. During subsequent high temperature processing the low diffusion coefficient drain-forming dopant remains concentrated near the top surface of the substrate while other well-forming dopants, including an adjacent channel-forming dopant, which have relatively higher diffusion coefficients, diffuse to deeper regions of the substrate. The slow-diffusing drain-forming dopant retards lateral widening of the channel by the faster-diffusing channel-forming dopant just below the substrate surface to at least the depth of the channel inversion layer formed under the channel surface during device turn on. Retardation of lateral channel growth just below the substrate surface results in an insulated gate device of reduced channel length and improved transconductance. In a preferred embodiment, the slow-diffusing drain-forming dopant is implanted on the substrate surface together with a fast-diffusing drain-forming dopant, and the latter is diffused to a pinch off depth below the substrate surface to counteract pinch off resistance between opposed segments of an adjacent shallow channel-forming well.

IGT and MOSFET devices having reduced channel width

A process for fabricating a power IC structure which includes the following masking steps:

Method of making a power IC structure with enhancement and/or CMOS logic

A disclosed MOSFET cell has a source region formed at the top surface of a semiconductor substrate. The top surface source region is electrically coupled to a conductive region at a bottom portion of the substrate by means of a vertical conduit which projects through the substrate from the top surface to the conductive region. A current exchanger is provided extending over the top surface of the substrate and coupling a top surface portion of the vertical conduit to the source region. The current exchanger makes ohmic contact with the source region and with the conduit region and shorts the two regions together such that majority carrier current of the conduit region will be 'converted' into majority carrier current of the source region and electrical continuity between the source region and the conductive region of the substrate is established. Respective source regions of multiple MOSFET cells may be interconnected in accordance with this method through a longitudinally extending conductive layer which is typically formed near the bottom surface of semiconductor substrates.

Mosfet structure with substrate coupled source

The construction of a semiconductor insulated gate device (IGT) is altered to avoid cell latching problems assisted with 'hot spot' sites where an atypically high density reverse current tends to flow. IGT cells adjacent these sites are totally or partially disabled by eliminating emitter regions therein to thereby remove any emitter-base junctions from the paths along which the high density reverse current flows. Also the area of emitter electrode ohmic contact is increased at these 'hot spot' sites to effectively divert reverse from neighboring, forward current conducting, active cells and thus reduce the density of reverse flow therethrough to safe levels.

Insulated gate device with configured emitter contact pad

A current limited insulated gate transistor (IGT) is disclosed wherein the individual cells are rectangular and each has four discrete, mutually spaced emitter regions to provide a reduced gate periphery. Each cell lacks emitter portions at the cell corners to reduce current crowding in the corner areas. The size of each cell is kept small to decrease the forward voltage drop of the IGT at its operating current level and the spacing between individual cells of the IGT is minimized in order to further reduce the maximum IGT current. These features enable the cell to survive a short-circuit load condition by preventing the maximum current from reaching the latch-up level.

Growing community of inventors

Raleigh, NC, United States of America

Hamza Yilmaz