Advanced Micro Devices Corporation

Cirrus Logic Inc.

Hamilton B Carter

William M Lowe

Tahsin Askar

Jelena Ilic

Paul W Berndt

Mike Lowe

Enrique Rendon

Mark LaVine

Joseph C Skrovan

Royce K Presley

The computational load of using a sequencer system and the memory allocation requirements demanded for sequencer operation are reduced in operation with functional models that do not require the services of a sequencer. The computational overhead introduced by the sequencer is reduced, and memory resources for a sequencer are diminished. Functional models that do not require sequencing are created with the same framework as functional models that do require sequencing, while eliminating the sequencer's computational overhead for functional models that do not require sequencing, and allowing functional models that to not require sequencing to be created without allocating the memory required to support the sequencer. Further, both sequenced and un-sequenced functional models coexist in the same sequenced verification framework, permitting the un-sequenced functional models to avoid the computational and memory allocation overhead otherwise incurred by the sequencer.

System and method for reducing computational overhead in a sequenced functional verification system

An event sequencer for a functional mechanism contains a list of signatures and corresponding priority designations, and an event list containing event information from race condition events that are to be re-ordered. A method for sequencing race condition events, includes storing signatures for identifying predetermined events, storing priority designations corresponding to the signatures to enable identification of relative priorities between identified events, detecting at least first and second events and information about each event, storing only upon signature match the events and event information associated with each event, sorting the events, and sending the sorted events to a functional mechanism. Events are compared with stored signatures, and signature matches are determined. The arrival of events is detected, events are compared with stored signatures, and matches between events and signatures are established.

Race condition ordering and functional verification system and method

A system and method for memory incoherent verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design receives a memory read stimulus from a stimulus file through a simulated first bus. The simulated model of the HDL design is configured to send its response to the stimulus onto a simulated second bus. A transaction checker receives the response from the simulated second bus and analyzes it to verify operation of the HDL design of the computer system component. The stimulus file and the transaction checker are both stored in the computer system memory. The simulated model's response to the memory read stimulus is evaluated by the transaction checker independently of any previous memory write stimulus from the stimulus file. There is no need to have a previous memory write operation or a master initialization of the system memory for every memory read operation. This enhances the sequences of operations that may be applied to a device under test. Multiple simulated models may read or write into the memory without timing constraints.

Memory incoherent verification methodology

A verification system and method for verifying operation of an HDL (Hardware Description Language) design of a computer system component are disclosed. The computer system is configured to interface between a first bus and second bus. During verification, a simulated model of the HDL design is coupled to a simulated first bus and a simulated second bus. A designated stimulus is applied to the simulated model through the simulated first bus. A stimulus file stored in the computer system memory is configured to specify the designated stimulus to be applied. In response to the designated stimulus, the simulated model initiates bus cycles on the simulated second bus. A transaction checker is provided in the computer system memory to receive information relating to these bus cycles from said simulated second bus. By employing two different busses--one to apply a stimulus and the other to resolve the bus cycle through transaction checking--an effective decoupling of test stimulus from the checking environment is achieved. Due to decoupling, the test environment can be made more robust, and can be used to generate random responses, remap memory, inject errors into data streams etc.

Verification strategy using external behavior modeling

A transaction checking system and method to verify bus bridge designs in multi-master bus systems. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a means of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures. Bus monitors may be employed along with the bus bridge model object to determine the values of the bus bridge configuration registers. This allows timing and other protocol related functionality of a system bus attached to the bus bridge to be verified without restricting the bus monitor to a specific bus bridge design (e.g., without requiring the bus monitors to maintain the net list names for the various configuration registers identified by the hardware description language representation of the bus bridge). Additionally, future bus bridge designs can also be tested in a device independent manner.

Bus bridge verification system including device independent bus monitors

A methodology that provides detection of cache coherency errors in addition to detection of inefficient cache use by a cache master is disclosed. A model of the cache with storage for the address and data contained in each cache line and a flag indicating the state of the cache line (e.g., MESI state, or other cache coherency protocol state) is utilized. In addition, the cache model object also holds a dynamically allocated list (the cycle list) of bus cycles. This list is used to store pointers to non-cache bus cycles initiated in the multi-bus system. Cache bus cycles can update the state of the cache model object and can also instruct the cache model to perform coherency tests on pending non-cache bus cycles in the cycle list. When all protocol tests for a non-cache bus cycle have been successfully completed, no further coherency tests are performed on that bus cycle. Cache master verification is also achieved by polling the cache model to determine source of target resolution cycles for a bus cycle initiated by bus masters. Thus, cache coherency and cache controller operations are efficiently checked.

Cache coherency detection in a bus bridge verification system

A system for and a method of monitoring the current state of a bus bridge in a device independent manner are disclosed. In a computer system having a bus bridge connecting a plurality of system buses, a bus bridge model object is created with storage space allocated for each of the bus bridge's configuration registers. A CPU write cycle state machine object may send bus cycles intended for the bus bridge to the bus bridge model also. Using the data from these cycles, the model updates its registers accordingly. Thus, the current state of the bus bridge is always known. In one embodiment, bus cycle state machine objects can also poll the bus bridge model object to determine if a bus cycle address is remapped by the bus bridge. Various bus objects, through their state machines, may also poll the bus bridge model for pertinent information. Hence, false failures because of a lack of knowledge of the state of the bus bridge can be eliminated and a tighter verification of bus bridge operations can be accomplished.

Bus bridge state monitoring in a bus bridge verification system

A method to track bus cycle data with byte granularity in a computer system with a bus bridge connecting a plurality of system buses is disclosed. The method eliminates false failures due to data merging performed by the bus bridge to enhance performance. A state machine model is created for each bus in the system. Each bus model is responsible for creating a bus cycle state machine object upon detecting an initiation of a corresponding bus cycle and storing it in an initiator or a target cycle list as the case may be. The bus cycle state machines are transitioned according to bus signals until a final state is reached--i.e. a state indicating that the bus protocol for the corresponding cycle was properly completed and only resolution of target data is pending. In this final state, initiator cycles compare their data bytes with those of target cycles only when they have common byte enables. These common byte enables may be deasserted upon finding of matching data bytes. Each initiator cycle remains in its final state until each byte of its data is accounted for.

Byte granularity data checking in a bus bridge verification system

A test methodology for a cache memory subsystem includes setting a test unit to initiate a snoop cycle on a local bus upon lapse of a predetermined delay. The predetermined delay is initially set to a very short delay or a zero delay. The snoop cycle to be executed may take the form of an inquire cycle to a predetermined memory address. The test unit is further set or programmed to begin monitoring the local bus for certain activity including activity which is indicative of whether the snoop cycle occurred. After programming the test unit, the processor core executes a memory operation associated with the address of the snoop cycle. This memory operation causes a cache line transition. At some point, either before, during or after effectuation of the memory operation, the snoop cycle is executed by the test unit in accordance with the predetermined delay. Upon completing the memory operation, a status register is read from the test unit to determine whether the snoop cycle has yet occurred. If the snoop cycle occurred prior to completing the memory operation, the predetermined delay is increased and the test is repeated for the increased delay. Prior to repeating the test, the cache line's coherency with external memory is checked for conformance with the cache protocol. Additionally, the test unit may further be programmed to detect an occurrence of certain external local bus signals generated by the cache memory subsystem, such as a signal indicating a hit to a cache line occurred, and a signal indicating that a hit to a modified line in the cache occurred. The test is repeated until it is determined that the snoop cycle has not occurred upon completion of the line fill instruction.

Cache coherency test system and methodology for testing cache operation

In a computer system having a bus bridge connecting a plurality of system buses, a methodology for checking completion of a bus cycle in a bus bridge verification system is disclosed. The methodology verifies that the bus bridge is asserting proper signals for each bus protocol. As each bus cycle begins, a state machine object corresponding to that bus cycle is instantiated and each byte of said bus cycle state machine object is checked for resolution. A stimulator object may provide a bus stimulus to said bus cycle state machine object which may update its states in response thereto. Upon transitioning into its holding state, the bus cycle state machine object may verify that each byte of its transaction is accounted for and has been routed to the proper destination. The state machine object for a particular bus cycle may contain storage for that bus cycle's properties such as clock cycle number, cycle address, cycle type, cycle data and the status of byte enables. This methodology maintains a static bus cycle object that can determine if its transaction has been resolved. The cycle-based approach avoids instances of false failures arising from address remapping, byte merging or byte collapsing.

State machine based bus cycle completion checking in a bus bridge

A method to correctly resolve combined data cycles in a bus bridge's posted write buffer is described. In a computer system with a bus bridge connecting a plurality of system buses, a state machine model is created for each bus in the system. A bus cycle state machine object corresponding to an initiated bus cycle is instantiated and stored in at least one of a plurality of cycle list objects. The combine cycle list stores combinable bus cycles and has number of entries equal to the number of entries in the posted write buffer. A pointer may be placed in the combine list upon creation of each combinable bus cycle. For each combinable cycle stored in it, the initiator cycle list searches the combine list for a cycle with an identical address and byte enable, but a later clock cycle number. This later cycle is matched its data with an appropriate target cycle in the target cycle list. Upon finding the data match, the initiator cycle list resolves the combinable initiator cycle. Thus, false failures due to byte collapsing can be eliminated.

Bus bridge transaction checker for correct resolution of combined data

In a computer system having a bus bridge connecting a plurality of system buses, a cycle list based bus cycle resolution checking system and method have been disclosed. Each bus in the system is treated as an individual, persistent object. Various bus cycles on system buses are also modeled as objects. Each bus object is configured to detect an initiation of a corresponding bus cycle. An initiator cycle list for holding bus cycles initiated by bus masters, and a target cycle list for storing bus cycles sent to bus targets are also created. Each cycle list itself is treated as an object. These cycle lists combinedly interact with a bus object to verify resolution of an initiator bus cycle. A stimulator object may provide a bus stimulus to each bus object as well as to each cycle list. The stimulator object may read said bus stimulus from a stimulus file of real or simulated buses. In such a case, bus bridge performance and functionality can be tested through externally simulated bus signals. Each bus object may instantiate a corresponding bus cycle state machine object upon detection of an initiated bus cycle and store it in the corresponding cycle list. Finally, the initiator cycle list may pass a pointer from each bus cycle state machine object in the target list to each initiator bus cycle state machine object to verify target data resolution for an initiator cycle.

Cycle list based bus cycle resolution checking in a bus bridge

A transaction checking system and method to verify bus bridges in multi-master bus systems are described. A state machine model is created for each bus in the system. An initiator cycle list and a target cycle list store corresponding bus cycle state machine objects and transition their states according to bus signals. The bus cycle state machines provide a mechanism of persistent storage for other verification tasks. A bus bridge model may store a copy of each configuration register for the bus bridge, thereby monitoring current state of the bus bridge. False failures due to data merging, data collapsing and address remapping are avoided. A cache model and a cycle-based messaging system provide verification of proper cache master operation. Cache coherency errors may also be detected. A statistics keeping object may be created to monitor and store all pertinent performance information for the bus bridge. The transaction checking system may monitor the state of the bus bridge in a device independent manner and with tighter verification. The cycle-based approach to verification of internal states of a bus bridge results in a sound resolution of bus cycles with a better predictability of possible failures.

Transaction checking system for verifying bus bridges in multi-master

A system and a method to monitor performance and resource utilization for a bus bridge in a computer system are described. All pertinent performance information for the bus bridge is stored in a statistics keeping or monitor object. A bus object is created for each bus in the system. Each bus cycle object receives the current cycle count and sends elapsed time information to the monitor object. A plurality of cycle list objects can also be used to track resource usage by sending messages to the monitor object indicating the type of cycles that enter the bus bridge. The monitor object then tracks the number of pending cycles that accumulate within the bus bridge. Thus, the statistics keeping object can indicate the current usage of each tracked resource.

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Austin, TX, United States of America

Hamilton B Carter