Nxp B.v.

Hamidreza Hashempour

Jos Verlinden

Ids Christiaan Keekstra

A clock delay circuit includes an output to provide an output clock signal which is a delayed version of an input clock signal. The clock delay circuit includes a latch whose output provides the output clock signal. A delay control circuit provides a third clock signal. The latch includes a first input to receive the input clock signal and a second input to receive the third clock signal. The amount of delay provided by the latch is dependent upon the duty cycle of the third clock signal.

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Eindhoven, Netherlands

Hamidreza Hashempour