Magma Design Automation, Inc.

Reflektion, Inc.

Envis Corporation

Hamid Savoj

David Berthelot

Timothy Michael Burks

Premal Buch

Robert Swanson

Lukas Van Ginneken

Michael A Riepe

Michael D Dixon

Emre Tuncer

Hsiao-Ping Tseng

Lukas P P P Van Ginneken

James D Tucek

Karen E Vahtra

Mercedes Mapua

Rajeev Madhavan

Patrick Mihelich

Win Min

Karen F Vahtra

A web page or group of pages can be automatically generated based on images selected by a user. The images are analyzed for color and groups of colors for the page background and image framing are determined. Images are analyzed to determine the shapes of the images and the images are placed within appropriate shapes on a page on the web. Click-through rate can be estimated for images and this click-through rate used during the web page generation. Important sections are evaluated in the images and cropping may occur for the images on a page. Text and video can be part of the web page. Software applications can be accessed from the web page as well. The online web pages can be tailored for presentation on a mobile device.

Image manipulation for web content

Techniques in which an optimal set of clock gating elements is determined for a selected circuit design. Those clock gating elements are coupled to selected flip-flops, with the effect that those selected flip-flops will consume less dynamic power during operation of the logic circuit. The selected set of clock gating elements provides an optimal savings in overall power consumption after modification of that selected circuit design.

Selection of optimal clock gating elements

A circuit &#x398; is coupled to an individual node N, in a circuit for which repeated logical values of that individual node can be identified as having a set of flip-flops Fdependent thereon, with the effect that if the individual node Nremains unchanged for one or more clock cycles, the set of dependent flip-flops Fcan be disabled for the second and succeeding clock cycles. The circuit &#x398; conditionally generates a clock-enabling signal Nin response thereto. One such circuit &#x398; conditionally includes a logical controller, whose output is coupled using a fan-out node to both an input to a state machine and a fan-in logic circuit (such as an AND gate). The flip-flop is clocked normally; its output is coupled to that same fan-in logic circuit, whose output Nis coupled to the set of dependent flip-flops F.

Clock gating by usage of implied constants

A method for modeling integrated circuit designs in a hierarchical design automation system which utilizes a block abstraction including therein set of all database objects (cells, nets, wires, vias, and blockages) that are necessary to achieve accurate placement, routing, extraction, simulation, and verification of the block's ancestors in the hierarchy.

Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system

A process for reducing cross-talk noise in a VLSI circuit is disclosed. The process identifies a victim net in an integrated circuit and calculates a change in ground capacitance for the victim net to identify a noise amplitude less than or equal to a maximum allowable noise height. The process selects from a library one cell or a grouping of cells having an input capacitance for the victim net closest to the change in ground capacitance. The selected cell or grouping of cells is coupled to the victim net so that its change in ground capacitance provides a noise amplitude less than (or less than or equal to) an allowable maximum noise height that may be a predetermined value. A system for reducing cross-talk noise in a VLSI circuit is also disclosed.

Reduction of cross-talk noise in VLSI circuits

What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a tinting budget by examining said generated arrival times at said block pins.

Method for generating design constraints for modules in a hierarchical integrated circuit design system

A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.

Timing optimization in presence of interconnect delays

Growing community of inventors

Los Altos, CA, United States of America

Hamid Savoj